Patents by Inventor Matthew Holliman

Matthew Holliman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20050108312
    Abstract: Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.
    Type: Application
    Filed: July 1, 2003
    Publication date: May 19, 2005
    Inventors: Yen-Kuang Chen, William Macy, Matthew Holliman, Eric Debes, Minerva Young
  • Patent number: 6816949
    Abstract: A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.
    Type: Grant
    Filed: January 3, 2002
    Date of Patent: November 9, 2004
    Assignee: Intel Corporation
    Inventors: Rainer W. Lienhart, Yen-Kuang Chen, Matthew Holliman, Minerva M. Yeung
  • Patent number: 6781589
    Abstract: An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: August 24, 2004
    Assignee: Intel Corporation
    Inventors: William W. Macy, Matthew Holliman, Eric Debes, Yen-Kuang Chen
  • Publication number: 20030126370
    Abstract: A cache management operation. In one embodiment, a first recall value for a first unit of data is generated, a second recall value for a second unit of data is generated, and the first and second recall values are compared. The unit of data having the higher recall value is stored in a first section of a storage device. The unit of data having the lower recall value is stored in a second section of a storage device. A greater amount of compression is performed on the unit of data having the lower recall value.
    Type: Application
    Filed: January 3, 2002
    Publication date: July 3, 2003
    Inventors: Rainer W. Lienhart, Yen-Kuang Chen, Matthew Holliman, Minerva M. Yeung
  • Publication number: 20030043156
    Abstract: An apparatus and method for extracting and loading data to/from a buffer are described. The method includes the selection of data from a data buffer in response to execution of a data access instruction. The data buffer includes a plurality of data storage devices, one or more of which initially contain the selected data. Accordingly, the plurality of data storage devices form a single address space that is addressable at a bit-level. When the selected data spans from a source data storage device to a next data storage device of the data buffer, a portion of the selected data from source data storage device is concatenated with a remaining portion of the selected data from the next data storage device to form the selected data as a contiguous unit. Finally, once the selected data is formed, the selected data is stored within a destination data storage device.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Inventors: William W. Macy, Matthew Holliman, Eric Debes, Yen-Kuang Chen