Abstract: A method for configuring a multiple input multiple output (MIMO) wireless communication begins by generating a first preamble for a first antenna of the MIMO communication, wherein the first preamble includes a carrier detect field, a first channel select field, a first signal field, and a second signal field. The method continues by generating a second preamble for at least one other antenna of the MIMO communication, wherein the second preamble includes the carrier detect field, a plurality of channel select fields, and the second signal field. The method continues by simultaneously transmitting the carrier detect field via the first antenna and the least one other antenna. The method continues by transmitting the first channel select field and the first signal field via the first antenna.

Abstract: A network interface includes a network medium interface operatively coupled to a software device driver arrangement, with a legacy media access controller (MAC) therebetween. The device driver arrangement includes a legacy MAC device driver configured to communicate with the legacy MAC, and an intermediate driver configured to communicate with the network medium interface. The intermediate driver and the network medium interface may communicate with one another by use of special frames, for example to send and receive control information. The special frames are formatted to pass through the legacy MAC, and include an identifier so that they can be identified at the intended destination, either the intermediate driver or the network medium interface. Upon identification, the control information is extracted at the destination. The network medium interface may include one or more MACs as well as one or more physical layer devices (PHYs).

Abstract: A method of testing a network physical layer device (PHY) having a media independent interface (MII) includes sending information between the PHY and a tester along the data buses of the MII. The information may be sent in the form of special frames, the special frames being sent from the tester to the PHY including an identifier. The PHY includes means for detecting the identifier, for extracting control information from the special frames, and for using the control information to execute write operations to and read operations accessing the memory registers of the PHY, and for sending information to the tester. The information may be passed between the PHY at an exemplary rate of 100 Mb/sec.

Abstract: A network interface examines a field of a successfully transmitted frame following a contention resolution and transmission ordering among a plurality of nodes contending for transmission of a frame. The field indicates whether the successfully transmitting node has any additional frames to transmit. The number of backoff slots is maintained at a current value, rather than decremented, if the field indicates that the successfully transmitting node has an additional frame to transmit. The next frame to be transmitted is assigned the highest backoff slot. This procedure avoids re-contention and re-ordering when the contending nodes have additional frames to transmit, thereby improving overall network performance.

Abstract: A networking interface device for coupling a system host having one of a plurality configurations to a network medium. The networking interface device has a peripheral component interconnect (PCI) interface for coupling the interface device to a system host configured with a PCI based system bus interface; a medium independent interface (MII) for coupling the interface device to a system host configured with a media access controller (MAC) based system bus interface; and a buffer management device (BMU) having an active state for bursting data packet traffic via the PCI interface when the interface device is coupled to a PCI based system bus interface and a passive state for continuously passing data packet traffic via the MII when the interface device is coupled to a MAC based system bus interface.

Abstract: A method and system for providing a low-level recovery of data on a communication network that provides an immediate negative acknowledgement of a data packet that contains bit errors, as determined by a receiving node on the network. The data packets contain two error detection mechanisms, with the first error detection mechanism being used by the receiving node to determine whether the data packet is uniquely addressed to that receiving node. When this is determined by the receiving node, the data payload is then checked to determine whether it contains a bit error. When an error is detected, the receiving node immediately sends out a negative acknowledgement, prior to the normal interframe spacing provided in network protocols, so that the transmitting node becomes aware that the data packet was not properly received at the receiving node. The transmitting node can then retransmit the data packet.

Abstract: A communications system is configured with a plurality of media terminal adapters, a telephone line, and a gateway configured to exchange voice and data packets between a network and each of the media terminal adapters over the telephone line. It is emphasized that this abstract is provided to comply with the rules requiring an abstract which will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or the meaning of the claims.

Abstract: A clock generating circuit is provided with a pair of programmable clock dividers coupled to a phase error detector for detecting a phase difference between signals corresponding to reference and clock signals. Frequency change logic produces a frequency adjustment signal that adjusts the frequency of the clock signal to eliminate the phase difference. The frequency adjustment signal is used to control a delay time in a first programmable delay chain. An updated frequency adjustment signal controls a delay time in a second programmable delay chain that receives an output signal of the first programmable delay chain. Signals delayed in the first and second programmable delay chains cause a stable clock signal at a variable frequency to be produced.

Abstract: A circuit is provided to convert an analog signal into a pulse signal, and simultaneously compress the analog signal. The input analog signal buffered by a sample-and-hold circuit is supplied to a chain of amplifier stages having equal gains greater than 1. A set of comparators compares the output signal of each amplifier stage with a reference value. As soon as the output of any amplifier stage exceeds the reference value, a logical summing device coupled to the comparators causes a pulse signal produced by the conversion circuit to become active. A clock signal controls the sample-and-hold circuit to produce a zero level sample-and-hold signal that causes the pulse signal to become inactive. As the amplifier chain is arranged so as to increase its total gain for a lower level of the input analog signal with respect to its total gain for a higher level of the input analog signal, the conversion circuit compresses the input analog signal simultaneously with its conversion into the pulse signal.

Abstract: A station in the WLAN monitors each transmitted frame to determine whether the frame transmission was protected by an existing outstanding airtime reservation. If a frame is transmitted without an airtime reservation and no response frame is received, the station assumes that the transmission failed due to contention, and monitors the number of contention attempts made to transmit each frame, and the number of failures to receive an acknowledgement. Based on this information, the station dynamically adjusts an RTS/CTS threshold used to determine whether or not an RTS/CTS exchange mechanism should be enabled. If a frame is transmitted during a time interval protected by an outstanding airtime reservation and no response frame is received, the station assumes that the transmission failed due to a bit error, and monitors the number of bit error rate (BER) attempts made to transmit each frame, and the number of BER failures to receive an acknowledgement.

Abstract: A wake-up system is provided to allow host computer access to a Card Information Structure (CIS) on a PCMCIA card during a SLEEP mode. The CIS is stored in a non-volatile memory accessible to a host computer via a PCMCIA bus and to PCMCIA card logic via a local bus. Arbitration logic is coupled between the PCMCIA and local buses to control access to the memory. Sleep logic prevents a fast clock signal from being supplied to the arbitration logic and the PCMCIA card logic when the PCMCIA card is switched into the SLEEP mode. A CIS read detect circuit decodes a CIS read operation on the PCMCIA bus and asserts the CIS detect signal supplied to the sleep logic. In response, the sleep logic allows the fast clock signals to be supplied to the arbitration logic and adapter card subsystem to exit from the SLEEP mode and provide the host computer with access to the memory storing the CIS information.

Abstract: A circuit is provided to carry out conversion and an analog signal into a digital signal, simultaneously with compression of the analog signal. An input analog signal buffered by a sample-and-hold circuit is supplied to a chain of amplifier stages having equal gains greater than 1. A set of comparators compares the output signal of each amplifier stage with a reference value. As soon as the output of any amplifier stage exceeds the reference value, an output of the corresponding comparator becomes active indicating the number of amplifier stages that were required to make the input signal higher than the reference value. A digital output device uses the comparator output signals to produce a digital signal proportional to the input signal level.

Abstract: A system is provided for ensuring that a ethernet controller operates to optimize bus latency and central processing unit (CPU) utilization in a network environment when reviewing data packets. Through the efficient use of a plurality of buffer memories and a driver, the bus utilization in conjunction with the controller the system provides for the receipt and transfer of data packets from the ethernet controller during the latency period of the network. In so doing, the overall performance of the network is enhanced.