Patents by Inventor Matthew M. Nowak
Matthew M. Nowak has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10039188Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.Type: GrantFiled: July 28, 2015Date of Patent: July 31, 2018Assignee: QUALCOMM IncorporatedInventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
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Patent number: 9813043Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: GrantFiled: March 24, 2016Date of Patent: November 7, 2017Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Patent number: 9672885Abstract: Systems, circuits and methods for controlling word line (WL) power levels at a WL of a Magnetoresistive Random Access Memory (MRAM). The disclosed power control scheme uses existing read/write commands and an existing power generation module associated with the MRAM to supply and control WL power levels, thereby eliminating the cost and increased die-size of schemes that control WL power through relatively large and expensive power control switches and control circuitry on the MRAM macro.Type: GrantFiled: September 4, 2012Date of Patent: June 6, 2017Assignee: QUALCOMM IncorporatedInventors: Sungryul Kim, Jung Pill Kim, Taehyun Kim, Seung H. Kang, Matthew M. Nowak, Manoj Bhatnagar
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Patent number: 9634640Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: GrantFiled: May 6, 2013Date of Patent: April 25, 2017Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Patent number: 9478528Abstract: Some implementations provide a semiconductor device that includes a first die and an optical receiver. The first die includes a back side layer having a thickness that is sufficiently thin to allow an optical signal to traverse through the back side layer. The optical receiver is configured to receive several optical signals through the back side layer of the first die. In some implementations, each optical signal originates from a corresponding optical emitter coupled to a second die. In some implementations, the back side layer is a die substrate. In some implementations, the optical signal traverses a substrate portion of the back side layer. The first die further includes an active layer. The optical receiver is part of the active layer. In some implementations, the semiconductor device includes a second die that includes an optical emitter. The second die coupled to the back side of the first die.Type: GrantFiled: February 20, 2013Date of Patent: October 25, 2016Assignee: QUALCOMM IncorporatedInventors: Kenneth Kaskoun, Shiqun Gu, Matthew M. Nowak
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Patent number: 9401689Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: GrantFiled: May 6, 2013Date of Patent: July 26, 2016Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Publication number: 20160204758Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: ApplicationFiled: March 24, 2016Publication date: July 14, 2016Inventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Patent number: 9331665Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: GrantFiled: May 6, 2013Date of Patent: May 3, 2016Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Patent number: 9203373Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.Type: GrantFiled: March 13, 2013Date of Patent: December 1, 2015Assignee: QUALCOMM IncorporatedInventors: Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Lan, Daeik D. Kim, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Publication number: 20150334847Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.Type: ApplicationFiled: July 28, 2015Publication date: November 19, 2015Inventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
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Patent number: 9101068Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.Type: GrantFiled: March 14, 2013Date of Patent: August 4, 2015Assignee: QUALCOMM INCORPORATEDInventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
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Patent number: 9024315Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.Type: GrantFiled: March 13, 2013Date of Patent: May 5, 2015Assignee: QUALCOMM, IncorporatedInventors: Hongjun Yao, Michael Laisne, Matthew M Nowak, Glen T Kim, Mark C Chan, Shiqun Gu
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Publication number: 20150035162Abstract: An inductive device that includes a conductive via and a metal layer are disclosed. A particular method of forming an electronic device includes forming a metal layer that contacts a surface of a substrate. The substrate, including the surface, is formed from a substantially uniform dielectric material. The metal layer contacts a conductive via that extends at least partially within the substrate. The metal layer and the conductive via form at least a portion of an inductive device.Type: ApplicationFiled: August 2, 2013Publication date: February 5, 2015Applicant: QUALCOMM IncorporatedInventors: Je-Hsiung Lan, Chengjie Zuo, Mario Francisco Velez, Daeik D. Kim, David F. Berdy, Changhan Yun, Robert P. Mikulka, Jonghae Kim, Matthew M. Nowak
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Publication number: 20140354372Abstract: Systems for reducing magnetic coupling in integrated circuits (ICs) are disclosed. Related components and methods are also disclosed. The ICs have a plurality of inductors. Each inductor generates a magnetic flux that has a discernible axis. To reduce magnetic coupling between the inductors, the flux axes are designed so as to be non-parallel. In particular, by making the flux axes of the inductors non-parallel to one another, magnetic coupling between the inductors is reduced relative to the situation where the flux axes are parallel. This arrangement may be particularly well suited for use in diplexers having a low pass and a high pass filter.Type: ApplicationFiled: September 6, 2013Publication date: December 4, 2014Applicant: QUALCOMM IncorporatedInventors: Chengjie Zuo, Jonghae Kim, Daeik D. Kim, Mario Francisco Velez, Changhan Yun, Je-Hsiung Lan, Robert P. Mikulka, Matthew M. Nowak
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Publication number: 20140327496Abstract: Tunable diplexers in three-dimensional (3D) integrated circuits (IC) (3DIC) are disclosed. In one embodiment, the tunable diplexer may be formed by providing one of either a varactor or a variable inductor in the diplexer. The variable nature of the varactor or the variable inductor allows a notch in the diplexer to be tuned so as to select a band stop to eliminate harmonics at a desired frequency as well as control the cutoff frequency of the pass band. By stacking the elements of the diplexer into three dimensions, space is conserved and a variety of varactors and inductors are able to be used.Type: ApplicationFiled: May 6, 2013Publication date: November 6, 2014Applicant: QUALCOMM IncorporatedInventors: Chengjie Zuo, Daeik D. Kim, Je-Hsiung Lan, Jonghae Kim, Mario Francisco Velez, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Patent number: 8866242Abstract: A memory device may comprise a magnetic tunnel junction (MTJ) stack, a bottom electrode (BE) layer, and a contact layer. The MTJ stack may include a free layer, a barrier, and a pinned layer. The BE layer may be coupled to the MTJ stack, and encapsulated in a planarized layer. The BE layer may also have a substantial common axis with the MTJ stack. The contact layer may be embedded in the BE layer, and form an interface between the BE layer and the MTJ stack.Type: GrantFiled: November 10, 2011Date of Patent: October 21, 2014Assignee: QUALCOMM IncorporatedInventors: Xia Li, Seung H. Kang, Matthew M. Nowak
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Publication number: 20140268615Abstract: A two-stage power delivery network includes a voltage regulator and an interposer. The interposer includes a packaging substrate having an embedded inductor. The embedded inductor includes a set of traces and a set of through substrate vias at opposing ends of the traces. The interposer is coupled to the voltage regulator. The two-stage power delivery network also includes a semiconductor die supported by the packaging substrate. The two-stage power delivery network also includes a capacitor that is supported by the packaging substrate. The capacitor is operable to provide a decoupling capacitance associated with the semiconductor die and a capacitance to reduce a switching noise of the voltage regulator.Type: ApplicationFiled: March 14, 2013Publication date: September 18, 2014Applicant: QUALCOMM INCORPORATEDInventors: Changhan Yun, Francesco Carobolante, Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Lawrence D. Smith, Matthew M. Nowak
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Publication number: 20140264331Abstract: An integrated circuit product package configured to continuity testing is described. The integrated circuit product package includes a package substrate. The package substrate includes internal routing connections. The integrated circuit product package also includes a semiconductor die coupled to the package substrate. The semiconductor die includes input/output (I/O) pins and switches. The switches selectively coupled the I/O pins to facilitate a daisy chain connection. The daisy chain connection includes circuitry fabricated on the semiconductor die, more than two of the internal routing connections, more than two of the I/O pins and at least one switch.Type: ApplicationFiled: March 13, 2013Publication date: September 18, 2014Applicant: QUALCOMM IncorporatedInventors: Hongjun Yao, Michael Laisne, Matthew M. Nowak, Glen T. Kim, Mark C. Chan, Shiqun Gu
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Publication number: 20140197902Abstract: A diplexer includes a substrate having a set of through substrate vias. The diplexer also includes a first set of traces on a first surface of the substrate. The first traces are coupled to the through substrate vias. The diplexer further includes a second set of traces on a second surface of the substrate that is opposite the first surface. The second traces are coupled to opposite ends of the set of through substrate vias. The through substrate vias and the traces also operate as a 3D inductor. The diplexer also includes a capacitor supported by the substrate.Type: ApplicationFiled: March 13, 2013Publication date: July 17, 2014Applicant: QUALCOMM INCORPORATEDInventors: Chengjie Zuo, Jonghae Kim, Mario Francisco Velez, Je-Hsiung Lan, Daeik D. Kim, Changhan Yun, David F. Berdy, Robert P. Mikulka, Matthew M. Nowak, Xiangdong Zhang, Puay H. See
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Publication number: 20140167273Abstract: One feature pertains to a multi-layer package substrate of an integrated circuit package that comprises a discrete circuit component (DCC) having at least one electrode. The DCC is embedded within an insulator layer, and a via coupling component electrically couples to the electrode. A first portion of the via coupling component extends beyond a first edge of the electrode, and a plurality of vias each having a first end couple to the first via coupling component. At least a first via of the plurality of vias couples to the first portion of the via coupling component that extends beyond the first edge of the electrode. Moreover, the plurality of vias each have a second end that electrically couple to a first outer metal layer, and at least a second portion of the via coupling component is positioned within a first inner metal layer.Type: ApplicationFiled: December 19, 2012Publication date: June 19, 2014Applicant: QUALCOMM INCORPORATEDInventors: Jonghae Kim, Chengjie Zuo, Changhan Yun, Mario Francisco Velez, Ravindra V. Shenoy, Matthew M. Nowak, Francesco Carobolante, Kyu-Pyung Hwang, Dong Wook Kim, Young K. Song