Patents by Inventor Matthew M. Ziegler
Matthew M. Ziegler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170004246Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.Type: ApplicationFiled: August 27, 2015Publication date: January 5, 2017Inventors: Christopher J. Berry, Lakshmi Reddy, Sourav Saha, Matthew M. Ziegler
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Publication number: 20170004243Abstract: A system and method of performing an intra-run decision during synthesis to determine a physical implementation of a system-on-chip (SoC) logic design are described. The method includes executing a stage of the synthesis with two or more scenarios, each scenario representing a unique combination of values of one or more parameters, and determining a quality measure associated with each of the two or more scenarios. The method also includes performing the intra-run decision by eliminating one or more of the two or more scenarios for execution in a subsequent stage of the synthesis based on the quality measure associated with each of the two or more scenarios.Type: ApplicationFiled: June 30, 2015Publication date: January 5, 2017Inventors: Christopher J. Berry, Lakshmi Reddy, Sourav Saha, Matthew M. Ziegler
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Patent number: 9529951Abstract: In one aspect, a method for tuning input parameters to a synthesis program is provided which includes the steps of: (a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function; (b) individually running synthesis jobs in parallel for each of the parameter settings in the subset; (c) analyzing results from a current iteration and prior iterations, if any, using the cost function; (d) using the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings; (e) running synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and (f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met.Type: GrantFiled: May 29, 2014Date of Patent: December 27, 2016Assignee: International Business Machines CorporationInventors: George D. Gristede, Matthew M. Ziegler
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Publication number: 20160147916Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.Type: ApplicationFiled: December 29, 2014Publication date: May 26, 2016Inventors: Hung-Yi Liu, Matthew M. Ziegler
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Publication number: 20160147932Abstract: A method and system are provided for tuning parameters of a synthesis program for a design description. The method includes (a) ranking individual parameter impact by evaluating a design-cost function of each of the parameters. The method further includes (b) creating a set of possible parameter combinations that is ordered by an estimated-cost function. The method additionally includes (c) selecting, from the set of possible parameter combinations, top-k scenarios having best estimated costs to form a potential set, and running at least some of the top-k scenarios in parallel through the synthesis program. The method also includes (d) repeating steps (b)-(c) for one or more iterations until at least one of a maximum iteration limit is reached and an exit criterion is satisfied.Type: ApplicationFiled: June 23, 2015Publication date: May 26, 2016Inventors: Hung-Yi Liu, Matthew M. Ziegler
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Publication number: 20150347641Abstract: In one aspect, a method for tuning input parameters to a synthesis program is provided which includes the steps of: (a) selecting a subset of parameter settings for the synthesis program based on a tuning optimization cost function; (b) individually running synthesis jobs in parallel for each of the parameter settings in the subset; (c) analyzing results from a current iteration and prior iterations, if any, using the cost function; (d) using the results from the current iteration and the prior iterations, if any, to create combinations of the parameter settings; (e) running synthesis jobs in parallel for the combinations of the parameter settings in a next iteration; and (f) repeating the steps (c)-(e) for one or more additional iterations or until an exit criteria has been met.Type: ApplicationFiled: May 29, 2014Publication date: December 3, 2015Applicant: International Business Machines CorporationInventors: George D. Gristede, Matthew M. Ziegler
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Patent number: 8954914Abstract: A layout for an integrated circuit is designed by assigning physical design attributes including locations to a selected subset of placeable objects in the circuit netlist, prior to any physical synthesis. A layout abstract is displayed in a graphical user interface to allow the designer to visually inspect a layout abstract which shows the selected objects at their assigned locations. After making any desired modifications to the object locations, the location information can be formatted as a synthesis input file. Physical synthesis is then carried out while maintaining fixed locations for the selected objects according to the assigned locations. Physical design attributes can include coordinates and an orientation. The selected subset of placeable objects can constitute an identified datapath of the integrated circuit design.Type: GrantFiled: April 2, 2013Date of Patent: February 10, 2015Assignee: International Business Machines CorporationInventors: John T. Badar, David W. Lewis, Michael H. Wood, Matthew M. Ziegler
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Patent number: 8839162Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.Type: GrantFiled: July 14, 2010Date of Patent: September 16, 2014Assignee: International Business Machines CorporationInventors: Michael D. Amundson, Dorothy Kucar, Ruchir Puri, Chin Ngai Sze, Matthew M. Ziegler
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Publication number: 20130326451Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.Type: ApplicationFiled: June 1, 2012Publication date: December 5, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Minsik Cho, Ruchir Puri, Haoxing Ren, Hua Xiang, Matthew M. Ziegler
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Patent number: 8566761Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.Type: GrantFiled: November 21, 2011Date of Patent: October 22, 2013Assignee: International Business Machines CorporationInventors: Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M Ziegler, Ruchir Puri
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Patent number: 8516412Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.Type: GrantFiled: August 31, 2011Date of Patent: August 20, 2013Assignee: International Business Machines CorporationInventors: Minsik Cho, Alvan W. Ng, Ruchir Puri, Haoxing Ren, Hua Xiang, Matthew M. Ziegler
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Patent number: 8495552Abstract: Latches and local-clock-buffers are automatically placed during integrated circuit physical synthesis. Prior to physically laying out the datapath, locations are assigned for the latches based on a logical representation of the datapath and on the fixed placements of pins. The computed latch locations optimize the datapath according to some predetermined criteria. Local-clock-buffers are also preplaced together with the latches further improving datapath performance.Type: GrantFiled: June 28, 2012Date of Patent: July 23, 2013Assignee: International Business Machines CorporationInventors: Minsik Cho, Ruchir Puri, Haoxing Ren, Hua Xiang, Matthew M. Ziegler
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Publication number: 20130132915Abstract: The present disclosure relates to a computer-based method and apparatus for determining datapath bit slices. A first two-way search is performed between an input vector and an output vector to identify gates in a datapath. A network flow is then constructed including the gates identified, and a min-cost max-flow algorithm is applied to the network flow to derive matching bit pairs between the input vector and the output vector. Next, the datapath bit slices are determined by performing a second two-way search between each of a starting bit in the input vector and an ending bit in the output vector of each of the matching bit pairs.Type: ApplicationFiled: November 21, 2011Publication date: May 23, 2013Applicant: International Business Machines CorporationInventors: Minsik Cho, Ruchir Puri, Haoxing Ren, Hua Xiang, Matthew M. Ziegler
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Publication number: 20130055176Abstract: In one embodiment, the invention is a method and apparatus for soft hierarchy-based synthesis for large-scale, high-performance circuits. One embodiment of a method for physically synthesizing a design of an integrated circuit includes compiling a logical description of the design into a flattened netlist, extracting a soft hierarchy from the flattened netlist, wherein the soft hierarchy defines a boundary on a die across which cells of the integrated circuit are permitted to move, and placing a cell of the integrated circuit on the die in accordance with the soft hierarchy.Type: ApplicationFiled: August 31, 2011Publication date: February 28, 2013Applicant: International Business Machines CorporationInventors: Minsik Cho, Alvan W. Ng, Ruchir Puri, Haoxing Ren, Hua Xiang, Matthew M. Ziegler
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Patent number: 8271920Abstract: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.Type: GrantFiled: August 25, 2010Date of Patent: September 18, 2012Assignee: International Business Machines CorporationInventors: Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler
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Publication number: 20120054699Abstract: Exemplary embodiments include a computer implemented method for large block and structured synthesis, the method including determining initial design data from starting points for a synthesis flow, receiving user-directed structuring is incorporated into the synthesis flow, applying logical synthesis on the initial design data, applying a physical design on the initial design data, determining whether circuit design parameters have been met and in response to circuit design parameters not being met, adjusting the circuit design parameters.Type: ApplicationFiled: August 25, 2010Publication date: March 1, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Minsik Cho, Victor N. Kravets, Smita Krishnaswamy, Dorothy Kucar, Jagannathan Narasimhan, Ruchir Puri, Haifeng Qian, Haoxing Ren, Chin Ngai Sze, Louise H. Trevillyan, Hua Xiang, Matthew M. Ziegler
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Publication number: 20120017186Abstract: Exemplary embodiments include a method for modifying a circuit synthesis flow having automated instructions, the method including receiving circuit design input for a circuit design, receiving custom specifications to the circuit design input, synthesizing high level logic from the circuit design input, placing logic on the circuit design, refining the circuit design and generating a circuit description from the circuit design.Type: ApplicationFiled: July 14, 2010Publication date: January 19, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael D. Amundson, Dorothy Kucar, Ruchir Puri, Chin Ngai Sze, Matthew M. Ziegler