Abstract: An approach to optimize specular highlight generation is presented. A single microprocessor instruction is used to generate an intensity value based upon a viewing angle value. An application stores a viewing angle value in an input register. When called, the “intensity instruction” retrieves the viewing angle value from the input register, and calculates an intensity value using three distinct steps. In turn, the intensity instruction stores the intensity value in an output register for the application to retrieve and further process. In one embodiment, the invention may be implemented using PowerPC™ assembly and VMX™ or Altivec™ instructions. In this embodiment, the intensity instruction may be represented as a “vspecefp” instruction, which stands for a “vector specular estimate floating point” instruction.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: The present invention is generally related to the field of image processing, and more specifically to an instruction set for processing images. Vector processing may involve rearranging vector operands in one or more source registers prior to performing vector operations. Typically, rearranging of operands in source registers is done by issuing a plurality of permute instructions that require excessive usage of temporary registers. Furthermore, the permute instructions may cause dependencies between instructions executing in a pipeline, thereby adversely affecting performance. Embodiments of the invention provide a level of muxing between a register file and a vector unit that allow for rearrangement of vector operands in source registers prior to providing the operands to the vector unit, thereby obviating the need for permute instructions.

Abstract: The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Abstract: The present invention is generally related to the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Abstract: The present invention is generally related to integrated circuit devices, and more particularly, to methods, systems and design structures for the field of image processing, and more specifically to vector units for supporting image processing. A dual vector unit implementation is described wherein two vector units are configured receive data from a common register file. The vector units may independently and simultaneously process instructions. Furthermore, the vector units may be adapted to perform scalar operations thereby integrating the vector and scalar processing. The vector units may also be configured to share resources to perform an operation, for example, a cross product operation.

Abstract: A process for transferring patterned non-densely packed interfacial particle films onto substrates by providing a substrate, modifying the substrate so that it is non-water wetting, providing an interfacial film of charged particles, applying a surface modifying procedure to said particles, and applying the interfacial particle film to the modified substrate to thereby form a patterned non-densely packed film on the substrate.

Abstract: An elongated protective textile sleeve for protecting elongate members and methods of constructing a fabric substrate therefore. The fabric substrate has a plurality of filamentary members either woven, knitted or braided with one another. At least some of the filamentary members of the substrate extend to cut edges and are fabricated of a multi-component material that includes a core of a first polymeric material and an outer sheath of a second polymeric material. The outer sheath is heat-fusible and the inner core is heat-settable. The outer sheaths of the filamentary members are heat fused at least in the regions near the cut edges to keep the cut edges from fraying or the filamentary members from pulling out of the substrate. The core is heat set to form the desired shape of the protective sleeve.

Abstract: A surveillance projectile consisting primarily of a very robust electronic device designed to be contained in a 40 mm cartridge that can be fired over distances through an open window or door and into a remote location, such as an enclosed site, where it is desirable to surreptitiously acquire intelligence by electronic means or by irradiating an interior with invisible infrared light to facilitate infrared sensing. The projectile may be configured to contain any of several types of surveillance devices. Such devices may be, but are not limited to, wirelessly operated cameras, audio transmitters, recorders and infrared illuminators. Audio transmission may be scrambled for decoding at a receiver.

Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Abstract: A method and apparatus are provided for implementing a power of two estimation function in a general purpose floating-point processor. A floating point number is stored within a memory. The floating point number includes a sign bit, a plurality of exponent bits, and a mantissa having an implied bit and a plurality of fraction bits. In response to a floating-point instruction, the mantissa is partitioned into an integer part and a fraction part, based on the exponent bits. A floating-point result is provided by assigning the integer part of the floating point number as an unbiased exponent of the floating-point result, and by utilizing combinational logic hardware for converting the fraction part of the floating point number to a fraction part of the floating point result.

Abstract: A strip component (12) is carried by a liner (52) into a storage spool (24) having spiral grooved flanges (36, 38) for edges of the liner (52) which are guided into the grooves by guide rods (66, 74) which do not interfere with the transporting of the strip component (12) into and out of the spool (24).

Abstract: An earth-boring bit for attachment to a drill string has rotatable cones with rows of cutting elements. The cutting elements are arranged in generally circumferential rows on each of the cones and interference fit into apertures in the shell surface. The rows include a heel row of cutting elements on the heel surface of each of the cones, and an adjacent row of adjacent row cutting elements next to the heel row cutting elements. Each heel row cutting element has at least one counterpart adjacent row cutting element that is spaced no farther from it than any other adjacent row cutting element, defining a proximal pair. Each of the cutting elements in each of the proximal pairs has a grip ratio, which is the barrel length divided by the diameter. Some of the proximal pairs having cutting elements with higher grip ratios than other cutting elements. None of the proximal pairs has both cutting elements with higher grip ratios.

Abstract: A tire (10) having a contoured precured bead filler or apex (40) with a contoured surface for directing the ply path (24A) of the cord reinforced carcass plies (24) is taught. The contour of the precured bead filler or apex (40) has a convex surface (42A) and concave surface (42B) that transition at an inflection location (T) at or below the rim flange (52) to which the tire (10) is to be mounted.

Abstract: An earth-boring bit has a bit body and at least one cantilevered bearing shaft depending inwardly and downwardly from the bit body. A cutter is mounted for rotation on the bearing shaft and includes a gage surface and an adjacent cutter backface. The cutter has negative offset with respect to the axis and direction of rotation of the bit. A plurality of cutting elements are arranged on the cutter including a plurality of gage cutting elements on the gage surface of the cutter. At least one of the gage cutting elements projects beyond the gage surface and defines a cutting surface facing the backface of the cutter for engaging the sidewall of the borehole being drilled as the gage cutting element moves up the sidewall.