Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: The present disclosure provides methods for detecting and identifying plant events that contain precision targeted genomic loci, and plants and plant cells comprising such targeted genomic loci. The method can be deployed as a high throughput process utilized for screening the intactness or disruption of a targeted genomic loci and optionally for detecting a donor DNA polynucleotide insertion at the targeted genomic loci. The methods are readily applicable for the identification of plant events produced via a targeting method which results from the use of a site specific nuclease.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: ESD safe ceramic component is provided which includes a sintered composition which is formed of a base material and a resistivity modifier. The base material includes a primary component and a secondary component, the primary component including Al2O3 and the secondary component including tetragonal-ZrO2.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: A semiconductor processing component includes a substrate and a layer overlying the substrate. The layer has a composition ReAyO1.5+2y, wherein Re is Y, La, a Lanthanoid series element, or a combination thereof, A is (Si1?aGea), 0.25?y?1.2, and 0?a?1.

Abstract: A Coulombic electrostatic chuck is disclosed which includes a substrate, a conductive layer overlying the substrate, and an arc elimination layer overlying the conductive layer. The electrostatic chuck further includes a high-k dielectric layer overlying the arc elimination layer, wherein the high-k dielectric layer has a dielectric constant of not less than about 10 and a resistivity of not less than about 1011 Ohm-cm.

Abstract: A method of changing the crystallographic orientation of a single crystal body is disclosed that includes the steps of characterizing a crystallographic orientation of the single crystal body and calculating a misorientation angle between a select crystallographic direction of the single crystal body and a projection of the crystallographic direction along a plane of a first exterior major surface of the single crystal body. The method further includes removing material from at least a portion of the first exterior major surface to change the misorientation angle.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: A microelectronic processing component can include a substrate and a corrosion-resistant layer. The substrate can include a metal-containing material, and the corrosion-resistant layer can be adjacent to the surface region. The corrosion-resistant layer can include a first portion and a second portion each including a rare earth compound, wherein the first portion is disposed between the substrate and the second portion, and the first portion has a first porosity, and the second portion has a second porosity that is greater than the first porosity. The component can be component within a processing apparatus used to process microelectronic workpieces. In a particular embodiment, the component can be exposed to the processing conditions as seen by the microelectronic workpiece when fabrication a microelectronic device from the microelectronic workpiece. Methods can be used to achieve the difference in porosity, and such methods can be for articles other than microelectronic processing components.

Abstract: A processing device includes a plurality of walls defining an interior space configured to be exposed to plasma and a surface coating on the interior surface of at least one of the plurality of walls. The surface coating includes pores forming interconnected porosity. The processing device further includes a sealant residing in at least a portion of the pores of the surface coating. In an embodiment, the sealant can be a thermally cured sealant having a cure temperature not greater than about 100° C. In another embodiment, the sealant can be an epoxy sealant having a viscosity of not greater than 500 cP in liquid precursor form. In yet another embodiment, the sealant can be a low shrinkage sealant characterized by a solidification shrinkage of not greater than 8%.

Abstract: This invention relates to a dense ceramics having ESD dissipative characteristics, tunable volume and surface resistivities in semi-insulative range (103-1011 Ohm-cm), substantially pore free, high flexural strength, light colors, for desired ESD dissipation characteristics, structural reliability, high vision recognition, low wear and particulate contamination to be used as ESD dissipating tools, fixtures, load bearing elements, work surfaces, containers in manufacturing and assembling electrostatically sensitive microelectronic, electromagnetic, electro-optic components, devices and systems.

Abstract: A composite material includes a polymer and a colloidal metal oxide. The composite material has a Plasma Etch Index of 40 relative to a polymer absent the colloidal metal oxide.

Abstract: An electrostatic chuck includes an insulating layer, a conductive layer overlying the insulating layer, a dielectric layer overlying the conductive layer, the dielectric layer having pores forming interconnected porosity, and a cured polymer infiltrant residing in the pores of the dielectric layer.

Abstract: A method of changing the crystallographic orientation of a single crystal body is disclosed that includes the steps of characterizing a crystallographic orientation of the single crystal body and calculating a misorientation angle between a select crystallographic direction of the single crystal body and a projection of the crystallographic direction along a plane of a first exterior major surface of the single crystal body. The method further includes removing material from at least a portion of the first exterior major surface to change the misorientation angle.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: A sapphire substrate includes a generally planar surface having a crystallographic orientation selected from the group consisting of a-plane, r-plane, m-plane, and c-plane orientations, and having a nTTV of not greater than about 0.037 ?m/cm2, wherein nTTV is total thickness variation normalized for surface area of the generally planar surface, the substrate having a diameter not less than about 9.0 cm.

Abstract: An electrostatic chuck is disclosed which includes a substrate, a patterned conductive layer overlying the substrate, such that the patterned conductive layer is defining electrode pathways separated by gaps. The electrostatic chuck also includes a resistive layer overlying the patterned conductive layer and a low-k dielectric layer overlying the substrate and disposed in the gaps between the electrode pathways. The low-k dielectric layer includes a material having a different phase than the material of the substrate.

Abstract: A Coulombic electrostatic chuck is disclosed which includes a substrate, a conductive layer overlying the substrate, and an arc elimination layer overlying the conductive layer. The electrostatic chuck further includes a high-k dielectric layer overlying the arc elimination layer, wherein the high-k dielectric layer has a dielectric constant of not less than about 10 and a resistivity of not less than about 1011 Ohm-cm.