Abstract: A weather sensing system mountable on a tubular member. The weather sensing system includes a weather sensor housing including removably attached first and second housing portions. The first housing portion includes a first open channel and the second housing portion including a second open channel aligned with and opening toward the first open channel. The first and second open channels form an enclosed channel for receiving and fixing the weather sensing system to the tubular member.

Abstract: A PLD includes a plurality of logic blocks, a test circuit, and a test pin set. The logic blocks are coupled to gating circuits that selectively adjust an operating voltage for the blocks in response to control signals. During operation of the PLD, the control signals are updated in response to externally-generated signals provided to the PLD via the test pin set and routed to the logic blocks using the test circuit.

Abstract: A method and apparatus are disclosed for reducing the likelihood of unintentionally or irreversibly activating one or more of a programmable logic device's output elements after a programming interruption. Output disable and enable bits are moved to near the beginning and end, respectively, of a programming bitstream, thereby maximizing the amount of time the device outputs are in high impedance mode during programming, and minimizing the risk of unintentionally driving the device outputs.

Abstract: A system and method for configuration of electronic devices using a smart card. A smart card configurable and testable system includes a programmable device, a bridge coupled to the programmable device, and a smart card interface coupled to the bridge. The bridge is configured and arranged to format configuration data from the smart card for transmission to the programmable device, and the smart card interface arrangement is configured and arranged to provide configuration data from the smart card to the bridge.

Abstract: An improved method for concurrently programming in-system programmable logic devices (PLDs). More specifically, where within a plurality of serially connected PLDs, there are devices having different numbers of programmable memory cells, and devices whose memory cells require different wait periods to carry out programming, the method herein provides more optimum time efficiency and uses significantly less time overall for programming, erasing or reading back the PLDs. Also, the invention accommodates the implementation of retries to assure complete programming or erasing even when the initial attempt is not entirely successful. The method provides steps for accommodating PLDs with different wait times by bypassing fully programmed devices and speeding up programming times after smaller and slower devices are programmed and larger and faster devices are still not fully programmed.