Abstract: A rotor system is provided in one example embodiment and may include a rotor duct; at least one rotor blade, wherein the at least one rotor blade comprises a tip end; and a multi-material tip extension affixed at the tip end of the at least one rotor blade, wherein the multi-material tip extension comprises an inboard portion fabricated from a first material and an outboard portion fabricated from a second material, wherein the second material is different than the first material.

Abstract: A method of calculating leg length discrepancy of a patient including: receiving patient bone data associated with a lower body of the patient; identifying anatomical landmarks in the patient bone data; orienting a first proximal landmark and a second proximal landmark relative to each other and an origin in a coordinate system; aligning a first axis associated with a first femur and a second axis associated with a second femur with a longitudinal axis extending in a distal-proximal direction, wherein the first and second distal landmarks are adjusted according to the alignment of the first and second axes; calculating a distance between the first and second distal landmarks in the distal-proximal direction along the longitudinal axis; and displaying at least one of the distance or a portion of the patient bone data on a display screen.

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

Abstract: A method of calculating leg length discrepancy of a patient including: receiving patient bone data associated with a lower body of the patient; identifying anatomical landmarks in the patient bone data; orienting a first proximal landmark and a second proximal landmark relative to each other and an origin in a coordinate system; aligning a first axis associated with a first femur and a second axis associated with a second femur with a longitudinal axis extending in a distal-proximal direction, wherein the first and second distal landmarks are adjusted according to the alignment of the first and second axes; calculating a distance between the first and second distal landmarks in the distal-proximal direction along the longitudinal axis; and displaying at least one of the distance or a portion of the patient bone data on a display screen.

Abstract: Techniques for generating a report for a website are presented herein. A method can include accessing, by one or more computing devices, a plurality of unidentified events. Each event in the plurality of unidentified events can be associated with one or more properties. Additionally, the method can calculate, using a machine-learned prediction model, a number of pseudo users associated with the plurality of unidentified events based on an event-to-user-ratio and a total number of unidentified events. Moreover, the method can include assigning a first event from the plurality of unidentified events to a first pseudo user based on the one or more properties of the first event. Furthermore, the method can include generating the report for the website. The report includes information derived from the first event being assigned to the first pseudo user.

Abstract: An example system includes first and second level memories and first and second memory controllers respectively coupled thereto. The system also includes a shadow cache associated with the second level memory and coupled to the second memory controller, which is also coupled to the first memory controller. In response to a generated read operation that includes a secure code, the second memory controller determines whether an address of the read operation matches an address that is tagged in the shadow cache; and determine whether the secure code of the read operation matches a secure code of a cache line hit by the read operation. The second memory controller then performs one of two sets of additional operations, depending on whether or not the address of the read operation matches the address tagged in the shadow cache and whether or not the secure code of the read operation matches the secure code of the cache line.

Abstract: In one embodiment, the present disclosure relates to a method of evaluating soft tissue tension surrounding a hip of a patient using navigation and software to track positions of the femur and a pelvis of the patient in real time. The method begins with intra-operative reduction of a femoral implant into an acetabulum of a patient and retrieval of first coordinates of a femoral head center of the femoral implant when the femoral implant is in a reduced position. Performance of a shuck test follows where the femur is distracted relative to the acetabulum. Retrieval of second coordinates of the femoral head center occurs when the femoral implant is distracted from the acetabulum, and a difference between the first coordinates and the second coordinates in a coronal plane is used to determine a shuck length vector.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

Abstract: A computer-implemented method is provided. The computer-implemented method generates a milling path for a tool of a surgical system, the milling path designed to enable the tool to resect material from a bone, the method including obtaining a model of the bone, intersecting an allowed volume with the model for defining a resection volume intended to be removed from the bone, and generating a plurality of sections. The method also includes, for a section, identifying a sub-volume of the resection volume corresponding to the section; generating milling path segments designed to enable the tool to remove the sub-volume of the resection volume; identifying, for the sub-volume of the resection volume, a region to be avoided by the tool; generating transition path segments designed to avoid the region; and generating the milling path by combining the milling path segments and the transition path segments.

Abstract: An apparatus includes a CPU core and a L1 cache subsystem including a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem including a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller configured to receive a read request from the L1 controller as a single transaction. Read request includes a read address, a first indication of an address and a coherence state of a cache line A to be moved from the L1 main cache to the L1 victim cache to allocate space for data returned in response to the read request, and a second indication of an address and a coherence state of a cache line B to be removed from the L1 victim cache in response to the cache line A being moved to the L1 victim cache.

Abstract: Provided is a zeroing target for a firearm sighting system that includes a range card insert and a range card sleeve. The range card insert includes zero range increment markings, caliber markings, and a point of aim indicator. The range card sleeve includes a zero range viewing window, a caliber viewing window, a point of aim viewing window, and a point of impact indicator. The range card insert fits within the range card sleeve and can be moved upwards or downwards within the sleeve for selecting a desired zero range increment marking and caliber marking. A laser boresight is aimed at the point of impact indicator and a sighting system on the weapon is adjusted until the sighting system is pointing at the point of aim indicator. When the two values align, the weapon is properly bore-sighted for the desired caliber and range, which can then be confirmed by live fire.

Abstract: An example circuit, e.g., an integrated circuit, comprises processor cores, each of which includes multiple memory blocks; power control circuits respectively coupled to the processor cores; isolation circuits respectively coupled to the processor cores; and controller circuitry coupled to each of the processor cores, to each of the power control circuits, and to each of the isolation circuits. The controller circuitry is configured to select a subset of processor cores of the processor cores and a subset of memory blocks of the subset of processor cores for testing; and cause non-selected memory blocks of the processor cores to be at least one of power gated, clock gated, and isolated from the selected subset of memory blocks.

Abstract: A method includes determining, by a level one (L1) controller, to change a size of a L1 main cache; servicing, by the L1 controller, pending read requests and pending write requests from a central processing unit (CPU) core; stalling, by the L1 controller, new read requests and new write requests from the CPU core; writing back and invalidating, by the L1 controller, the L1 main cache. The method also includes receiving, by a level two (L2) controller, an indication that the L1 main cache has been invalidated and, in response, flushing a pipeline of the L2 controller; in response to the pipeline being flushed, stalling, by the L2 controller, requests received from any master; reinitializing, by the L2 controller, a shadow L1 main cache. Reinitializing includes clearing previous contents of the shadow L1 main cache and changing the size of the shadow L1 main cache.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: An arrangement for influencing liquid flow comprises a first section selectively configurable to provide a vortex generator surface to induce vortices in the liquid flow. The arrangement further comprises a second section, wherein the first section and second section are movable relative to one another to provide the vortex generator surface.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: A device includes memory blocks; connections respectively coupled to the memory blocks; and control logic coupled to the memory blocks. The control logic is operable to control performance of error-related transactions on the memory blocks via the connections. Such control may include causing a first error-related transaction to be performed on a first memory block of the memory blocks during a first time period, causing a second error-related transaction to be performed on a second memory block of the memory blocks during a second time period, and causing a transaction that is not an error-related transaction to be performed on at least one of the memory blocks, except the first memory block, during performance of one or both of the first error-related transaction and the second error-related transaction.

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions.

Abstract: An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.