Abstract: Systems and methods are provided for presenting subtitles. The systems and methods include accessing, by a user device, a video discovery graphical user interface that includes a plurality of videos; receiving a user input that gradually reduces volume of the user device; determining that the volume of the user device has gradually been reduced by the user input until a mute state has been reached in which audio output of the user device is disabled; and in response to determining that the volume of the user device has gradually been reduced until the mute state has been reached, automatically causing subtitles of a first video of the plurality of videos to be displayed during playback of the first video.

Abstract: A system includes a non-coherent component; a coherent, non-caching component; a coherent, caching component; and a level two (L2) cache subsystem coupled to the non-coherent component, the coherent, non-caching component, and the coherent, caching component. The L2 cache subsystem includes a L2 cache; a shadow level one (L1) main cache; a shadow L1 victim cache; and a L2 controller. The L2 controller is configured to receive and process a first transaction from the non-coherent component; receive and process a second transaction from the coherent, non-caching component; and receive and process a third transaction from the coherent, caching component.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: An integrated circuit comprises a set of processor cores, wherein each processor core of the set of processor cores includes BIST logic circuitry and multiple memory blocks coupled to the BIST logic circuitry. Each processor core further includes multiple power control circuitry, where each power control circuitry of the multiple power control circuitry is coupled to a respective processor core of the set of processor cores, multiple isolation circuitry, where each isolation circuitry of the multiple isolation circuitry is coupled to a respective processor core of the set of processor cores, a built-in-self repair (BISR) controller coupled to the each of the set of processor cores, each of the multiple power control circuitry, and each of the multiple isolation circuitry, and a safety controller coupled to the BISR controller, the multiple power control circuitry, and to the multiple isolation circuitry.

Abstract: An apparatus includes a central processing unit (CPU) core and a cache subsystem coupled to the CPU core. The cache subsystem includes a first memory, a second memory, and a controller coupled to the first and second memories. The controller is configured to execute a sequence of scrubbing transactions on the first memory and execute a functional transaction on the second memory. One of the scrubbing transactions and the functional transaction are executed concurrently.

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.

Abstract: A lighted accessory and/or corresponding method of installation seamlessly replace an original equipment manufacturer (OEM) lighting apparatus and/or accessory. The accessory includes a front side and back side with a circuit board positioned therebetween. One side of the accessory includes translucent portion(s). The circuit board includes a plurality of light emitting diodes (LEDs) which are aligned with the translucent portion of the front side of the accessory such that when the LEDs are illuminated, light is emitted from the accessory. The circuit board also includes at least one microcontroller and a radio-frequency interference filter circuit wherein the microcontroller controls the LEDs and the radio-frequency interference filter circuit mitigates RF emissions.

Abstract: In one embodiment, the present disclosure relates to a method of evaluating soft tissue tension surrounding a hip of a patient using navigation and software to track positions of the femur and a pelvis of the patient in real time. The method begins with intra-operative reduction of a femoral implant into an acetabulum of a patient and retrieval of first coordinates of a femoral head center of the femoral implant when the femoral implant is in a reduced position. Performance of a shuck test follows where the femur is distracted relative to the acetabulum. Retrieval of second coordinates of the femoral head center occurs when the femoral implant is distracted from the acetabulum, and a difference between the first coordinates and the second coordinates in a coronal plane is used to determine a shuck length vector.

Abstract: In an embodiment, a duct for a ducted-rotor aircraft includes a hub, the hub including a rotor and one or more motors configured to drive the rotor. The duct also includes a duct ring that defines an opening surrounding at least a portion of the hub. The duct also includes a plurality of stators that extend outward from the hub. The duct also includes at least one battery electrically coupled to the rotor and configured to power the one or more motors.

Abstract: A method for online authentication includes receiving membership authenticating information specific to members of a particular affiliation from the members and from one or more remote databases. The information is aggregated and stored in an aggregate database. An individual is authenticated, via a widget at least one of integrated into, and accessible by, at least one of a mobile application and a website of a provider of at least one of a particular program and a particular service, as a member of the particular affiliation based on a comparison of authenticating indicia provided online by the individual and the information stored in at least one of the aggregate database and the remote databases. Digital credentials are provided to the individual for access to the at least one of the particular program and the particular service when the individual is authenticated. The credentials include a unique identifier, a login and password.

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

Abstract: In described examples, a processor system includes a processor core that generates memory write requests, a cache memory, and a memory pipeline of the cache memory. The memory pipeline has a holding buffer, an anchor stage, and an RMW pipeline. The anchor stage determines whether a data payload of a write request corresponds to a partial write. If so, the data payload is written to the holding buffer and conforming data is read from a corresponding cache memory address to merge with the data payload. The RMW pipeline has a merge stage and a syndrome generation stage. The merge stage merges the data payload in the holding buffer with the conforming data to make merged data. The syndrome generation stage generates an ECC syndrome using the merged data. The memory pipeline writes the data payload and ECC syndrome to the cache memory.

Abstract: Embodiments disclosed herein generally relate to a system and method of verifying an identity of user. A computing system receives a HTTP request. The HTTP request includes at least a user name and an IP address associated with a router accessed by the remote client device. The computing system parses the HTTP request to extract the user name and the IP address contained therein. The computing system identifies a user account associated with the extracted user name. The computing system identifies an internet service provider associated with the IP address. The computing system transmits a verification message to the third party service provider. The computing system receives a confirmation message from the third party service provider. The computing system increases a level of confidence in an identification verification process based on the confirmation.

Abstract: An apparatus includes a CPU core, a first cache subsystem coupled to the CPU core, and a second memory coupled to the cache subsystem. The first cache subsystem includes a configuration register, a first memory, and a controller. The controller is configured to: receive a request directed to an address in the second memory and, in response to the configuration register having a first value, operate in a non-caching mode. In the non-caching mode, the controller is configured to provide the request to the second memory without caching data returned by the request in the first memory. In response to the configuration register having a second value, the controller is configured to operate in a caching mode. In the caching mode the controller is configured to provide the request to the second memory and cache data returned by the request in the first memory.

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

Abstract: A pickup full of gear doesn't have to be a jumbled mess. A modular, lightweight load-carrying system is custom engineered to fit directly onto a tailgate using the existing OEM mounting points of the vehicle. The rack systems allow drivers of the vehicle to keep gear organized, easily accessible, and secure.

Abstract: A contextual menu system may be configured to perform operations that include: identifying a media category based on a user profile, the user profile comprising user profile data; causing display of a GUI that includes a content menu, the content menu comprising at least a display of a set of media items associated with the media category identified based on the user profile data, the set of media items comprising at least a first media item; accessing the user profile data of the user profile, the user profile data including a browser history associated with the user profile; identifying the first media item among the browser history; and removing the content menu within the GUI in response to the identifying the first media item among the browser history.

Abstract: A rotor system includes a rotor duct; at least one rotor blade that includes an outboard end; a tip extension mechanism affixed at the outboard end of the at least one rotor blade, the tip extension mechanism including at least one shim, the at least one rotor blade with the tip extension mechanism affixed thereto including an extended rotor blade; and a blade tip affixed to an outboard end of the extended rotor blade, wherein the blade tip is affixed to the extended rotor blade via at least one removable fastener.

Abstract: An apparatus includes a CPU core, a first memory cache with a first line size, and a second memory cache having a second line size larger than the first line size. Each line of the second memory cache includes an upper half and a lower half. A memory controller subsystem is coupled to the CPU core and to the first and second memory caches. Upon a miss in the first memory cache for a first target address, the memory controller subsystem determines that the first target address resulting in the miss maps to the lower half of a line in the second memory cache, retrieves the entire line from the second memory cache, and returns the entire line from the second memory cache to the first memory cache.