Patents by Inventor Matthias A. Blumrich

Matthias A. Blumrich has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040073758
    Abstract: A low latency memory system access is provided in association with a weakly-ordered multiprocessor system. Each processor in the multiprocessor shares resources, and each shared resource has an associated lock within a locking device that provides support for synchronization between the multiple processors in the multiprocessor and the orderly sharing of the resources. A processor only has permission to access a resource when it owns the lock associated with that resource, and an attempt by a processor to own a lock requires only a single load operation, rather than a traditional atomic load followed by store, such that the processor only performs a read operation and the hardware locking device performs a subsequent write operation rather than the processor. A simple prefetching for non-contiguous data structures is also disclosed.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 15, 2004
    Inventors: Matthias A. Blumrich, Dong Chen, Paul W Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Dirk Hoenicke, Martin Ohmacht, Burkhard D. Steinmacher-Burow, Todd E. Takken, Pavlos M. Vranas
  • Publication number: 20040068599
    Abstract: A system and method for generating global asynchronous signals in a computing structure. Particularly, a global interrupt and barrier network is implemented that implements logic for generating global interrupt and barrier signals for controlling global asynchronous operations performed by processing elements at selected processing nodes of a computing structure in accordance with a processing algorithm; and includes the physical interconnecting of the processing nodes for communicating the global interrupt and barrier signals to the elements via low-latency paths. The global asynchronous signals respectively initiate interrupt and barrier operations at the processing nodes at times selected for optimizing performance of the processing algorithms.
    Type: Application
    Filed: August 22, 2003
    Publication date: April 8, 2004
    Inventors: Matthias A. Blumrich, Dong Chen, Paul W. Coteus, Alan G. Gara, Mark E. Giampapa, Philip Heidelberger, Gerard V. Kopcsay, Burkhard D. Steinmacher-Burow, Todd E. Takken
  • Patent number: 6020315
    Abstract: A preparation having increased in vivo tolerability comprising a glycosyl-Y[--C(.dbd.Y)--X--].sub.p --W(R).sub.n --X--C(.dbd.Y)-active compound, sugar or sugar alcohol and, optionally divalent ions, and a pharmaceutically tolerable carrier.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: February 1, 2000
    Assignee: Hoechst Aktiengesellschaft
    Inventors: Klaus Bosslet, Jorg Czech, Manfred Gerken, Rainer Straub, Matthias Blumrich