Abstract: Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

Abstract: A hard mask is produced from spacer structures. The spacer structures are formed from a conformal deposition on elevated structures produced lithographically in a projection process. The conformal deposition is etched back laterally on the elevated structures resulting in the spacer structures. The elevated structures between the spacer structures are subsequently etched away, so that the spacer structures remain in an isolated fashion as sublithographic structures of a hard mask with a doubled structure density compared with that originally produced in lithographic projection. In a regularly disposed two-dimensional array of structures in the hard mask for forming trenches—for instance for trench capacitors—the method achieves a doubling of the structure density in the array. A further iteration step is formed by forming further spacer structures on the first and second spacer structures, thereby achieving an even higher increase in structure density in the hard mask.

Abstract: The invention relates to a method for fabricating low-resistance electrodes in trench capacitors, and includes steps of: providing a wafer; producing trenches in the wafer; introducing the wafer into an electrolyte solution including a salt of an electrically conductive material; and electrically contact-connecting the wafer and applying a voltage between the wafer and a counterelectrode configured in the electrolyte solution to electrodeposit at least sections of the electrically conductive material in the trenches. The electrodeposition of the electrode material enables a uniform layer thickness along all regions of the trench wall.

Abstract: The invention relates to a method for trench etching, in particular a method for anisotropic deep trench (DT) etching in an Si substrate by plasma dry etching, such as reactive ion etching (RIE), magnetically enhanced RIE or inductively coupled plasma etching (ICP), and sidewall passivation of the etched trenches in the Si substrate, the Si substrate being provided with an etching mask before the beginning of the etching operation.

Abstract: A contact spring configuration for contacting semiconductor wafers is provided. At least one strip-type contact spring is provided on a substrate. The contact spring is fixed to a surface of the substrate on one side and is composed of a semiconductor material having a stress gradient which causes a permanent bending of the contact spring. The stress gradient in the semiconductor material is brought about by two semiconductor layers which are connected to one another and are mechanically strained differently. The different strains can be set by different doping or by deposition temperatures of different magnitude during the deposition of the semiconductor layers. The contact springs provide a good ohmic contact in particular with contact regions of a semiconductor wafer that are composed of a semiconductor material.

Abstract: A method for roughening a surface of a semiconductor substrate includes the steps of placing the substrate in a furnace, introducing Oxygen and an inert gas, such as argon or nitrogen, into the furnace, maintaining the oxygen concentration in the furnace below 10%, and annealing the substrate at a temperature between 950° C. and 1200° C. to form mesopores in the surface of the semiconductor substrate.

Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

Abstract: A trench capacitor has a first capacitor electrode, a second capacitor electrode, and a dielectric, which is arranged between the capacitor electrodes. The first capacitor electrode has a tube-like structure, which extends into a substrate. The second capacitor electrode includes a first section which is opposite to the internal side of the tube-like structure, with the dielectric arranged therebetween, and a second section, which is opposite to the external side of the tube-like structure with the dielectric arranged therebetween.

Abstract: A storage cell field has a plurality of storage cells formed in a substrate of a first doping type, said storage cells comprising a trench capacitor arranged in said substrate and a selection transistor associated with said trench capacitor and provided with a transistor body which is arranged in said substrate. An implantation having an increased dopant concentration of the first doping type is provided in said substrate. This implantation prevents space-charge zones, which are located at the trench capacitors and which are caused in predetermined storage states of said trench capacitors, from constricting a substrate region, which is available for applying a predetermined potential to the transistor bodies, in such a way that said predetermined potential cannot be applied.

Abstract: It is proposed when forming field-effect transistor devices in a semiconductor substrate for the overlapping region of a source-drain region that is to be provided to be formed directly as a material region, in particular with outdiffusion processes being avoided to the greatest extent. This takes place in particular by forming the connection region or buried-strap region as selectively epitaxially grown-on single-crystal, possibly doped silicon.

Abstract: An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM as simply as possible by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof, and then providing at least part of the widened region with a material region for the insulation region.

Abstract: In a process for the electrochemical oxidation of a semiconductor substrate that has recesses, such as for example, capacitor trenches or mesopores, formed in a silicon surface region, self-limited oxide formation takes place. The end of this formation is reached as a function of the process parameters such as the doping of the silicon region, the applied voltage and the composition of the electrolyte used, as soon as either a predetermined maximum layer thickness of the formed oxide or a predetermined minimum residual silicon layer thickness between two adjacent recesses is reached. The self-limiting is achieved either as a result of the overall voltage applied over the silicon oxide layer, which has already formed, dropping or as a result of the space charge regions of adjacent recesses coming into contact with one another.

Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: A method for electrically contacting a rear side of a semiconductor substrate when processing the semiconductor substrate includes the step of placing the semiconductor substrate with a substrate rear side on a substrate holder such that an electrically conductive contact layer formed of a semiconductor material is disposed between the semiconductor substrate and the substrate holder.