Abstract: A method for providing interlocking strained silicon on a silicon substrate, comprises providing a mask on a surface of the substrate. The mask comprises a first plurality of openings corresponding to a first plurality of holes to be etched and comprises a second plurality of openings corresponding to a second plurality of holes to be etched. The surface of the substrate is etched through the mask to form the first and second pluralities of holes. A first strain type material is deposited into the first plurality of holes to form a plurality of first strain type portions. A plurality of second strain type portions are formed at the second plurality of holes.

Abstract: A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

Abstract: The upper capacitor electrode of the trench capacitor is connected to an epitaxially grown source/drain region of the select transistor by a tubular, monocrystalline Si contact-making region. The gate electrode layer has an oval peripheral contour around the transistor, the oval peripheral contours of the gate electrode layers of memory cells arranged in a row along a word line forming overlap regions in order to increase the packing density.

Abstract: A method fabricates a semiconductor structure having a plurality of memory cells that are provided in a semiconductor substrate of a first conductivity type and contains a plurality of planar selection transistors and a corresponding plurality of storage capacitors connected thereto. The selection transistors have respective first and second active regions of a second conductivity type. The first active regions are connected to the storage capacitors and the second active regions are connected to respective bit lines, and respective gate stacks, which are provided above the semiconductor substrate in a manner insulated by a gate dielectric. In this case, a single-sided halo doping is effected, and an excessive outdiffusion of the halo doping zones is prevented by introduction of a diffusion-inhibiting species.

Abstract: An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a second gate dielectric. The second gate dielectric includes an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.

Abstract: Methods of fabricating an integrated circuit, in particular a dynamic random access memory are described. After forming memory cells on a semiconductor substrate a mirror layer is provided, said mirror layer covering the memory cells. Then logic devices are formed adjoining to said memory cells covered by said mirror layer, said forming of said logic devices including activating the dopants in dopant regions by means of a radiation annealing, said radiation being reflected by said mirror layer. After at least partly removing the mirror layer; a wiring of the memory cells and of the logic devices is formed.

Abstract: The present invention provides a fabrication method for a semiconductor structure and a corresponding semiconductor structure.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.

Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

Abstract: The present invention refers to a trench capacitor structure as it is used in memory cells, for example in memory cells of memory devices. Particularly, the capacitor structure may be used in a DRAM memory. Furthermore, the invention relates to a memory cell comprising a transistor and a capacitor with a trench capacitor structure arranged in a semiconductor substrate. Furthermore, the invention relates to a DRAM comprising a memory cell with a transistor and a capacitor, whereby the capacitor comprises a trench capacitor structure. Moreover, the invention relates to a method for forming a capacitor structure in a semiconductor substrate.

Abstract: Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

Abstract: The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure.

Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

Abstract: A method for manufacturing contact structures for DRAM semiconductor memories is disclosed. In one embodiment, contact openings are formed in a support area after execution of high-temperature processes for activating doping agents and repairing crystal defects. A low contact resistance between a conductive contact opening filling and an adjacent semiconductor substrate is achieved by forming a cobalt silicide or nickel silicide.

Abstract: In a method for patterning a semiconductor component a first cover layer is applied to a first region and a second region of a semiconductor component being arranged in a semiconductor substrate. The first region is different from the second region. The first cover layer is patterned using a photolithographic mask so that the first region is uncovered and the second region remains covered by the first cover layer. The first region is uncovered, a second cover layer is applied to the uncovered first region, and the first cover layer is removed so that the second region is uncovered. The uncovered second region is then doped.

Abstract: Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

Abstract: A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1?x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection is enabled.

Abstract: Spacer structures of field effect transistor structures are enhanced at least in sections with immobile charge carriers. The charge accumulated in the spacer structures induces an enhancement zone of mobile charge carriers in the underlying semiconductor substrate. The enhancement zone reduces the resistance of a channel coupling between the respective source/drain region and a channel region of the respective field effect transistor structure, wherein the channel region being controlled by a potential of a gate electrode. Source/drain regions drawn back from the gate electrode of the field effect transistor structure reduce an overlap capacitance between the gate electrode and the respective source/drain regions. A method for fabricating transistor arrangements having n-FETs and p-FETs with enhanced spacer structures.