Abstract: A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

Abstract: A system, method, and apparatus are provided for verifying functional safety of an image signal processor (ISP) by configuring one or more edge pattern settings in a test pattern generator; activating the test pattern generator to generate test pattern data by modulating a sequence of pseudo random number values with a sequence of values from an edge pattern; processing the test pattern data at the ISP to generate ISP test output data; generating a checksum value of the ISP test output data; and comparing the checksum value with a reference checksum value to verify a functionality of the ISP.

Abstract: Distortion correction from a distorted source image to a distortion corrected target image includes dividing the target image into a plurality of target tiles. The source image is divided into source tiles. Each source tile corresponds to a target tile according to a first mapping. The source tiles are processed to produce a source tile index until all the source tiles in the source image have been assigned a source tile index value in an ascending order. At least one y coordinate value of a first target tile is higher than a y coordinate value of a second target tile, wherein the first target tile corresponds to a source tile that appears earlier in the ascending order of the source tile index than a corresponding source tile of the second target tile. Distortion correction of the source image is performed by mapping each source tile to its corresponding target tile.

Abstract: A system, method, and apparatus are provided for on-the-fly camera image processing configuring a system-on-chip (SoC) configuration register memory with one or more synchronization settings; processing multiple camera image frame sequences having different specified exposures to detect a set of complete frames from the camera image frame sequences which have a first common frame number; identifying a valid combination of different exposures from the image frame sequences having a second common frame number succeeding the first common frame number; and processing the valid combination of different exposures from the first and second camera image frame sequences to generate output data from the ISP pipeline.

Abstract: Aspects of the subject disclosure may include, for example, splitting an image that is obtained from a video adaptor into a plurality of segments, for each segment of the plurality of segments, generating a value that is representative of data of the segment, the value resulting in no loss in an accuracy of the data, storing a first part of the value in a first portion of a memory, and storing a second part of the value in a second portion of the memory, the second part being different from the first part. Other embodiments are disclosed.

Abstract: The present disclosure relates to a laundry treating apparatus that has an apparatus that separates foreign matters attached to a heat exchanger such as a condenser and an evaporator, wherein the apparatus is able to provide a mechanical force for separating the foreign matters from the heat exchanger.

Abstract: Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.

Abstract: A system-on-chip (SoC) includes first and second processing circuits and a data exchange circuit such that the first processing circuit is configured to process image lines based on corresponding sets of processing attributes. The first processing circuit is further configured to continuously receive and process the image lines one after the other to generate corresponding output data, and the second processing circuit is configured to continuously receive by way of the data exchange circuit, the generated output data for processing the generated output data. The data exchange circuit is thus configured to control data flow between the first processing circuit and the second processing circuit such that the first processing circuit and the second processing circuit parallelly process corresponding data associated with same or different image lines.

Abstract: A system for processing multiple images includes an access serializer, trigger controllers, a first-in-first-out (FIFO) memory, and an image signal processing (ISP) pipeline circuit. The access serializer serializes access requests that are associated with processing of input image lines of the images. The trigger controllers decode corresponding serialized access requests to generate trigger identifiers (IDs), respectively. The FIFO memory receives a corresponding trigger ID from each trigger controller and provides the trigger IDs to the ISP pipeline circuit based on an order of reception of the trigger IDs. The ISP pipeline circuit receives the input image lines associated with the trigger IDs, and based on a corresponding set of configuration parameters associated with the input image lines, processes the input image lines in an order of reception of the trigger IDs, to generate processed image lines, respectively.

Abstract: Embodiments provide line-based feature generation for vision-based driver assistance systems and methods. For one embodiment, a feature generator includes a circular buffer and a processor coupled to an image sensor. The circular buffer receives image data from the image sensor and stores N lines at a time of an image frame captured by the image sensor. The N lines of the image frame are less than all of the lines for the image frame. The processor receives the N lines from the circular buffer and stores one or more features generated from the N lines in a memory. Iterative blocks of N lines of image data are processed to complete processing of the full image frame, and multiple frames can be processed. The generated features are analyzed by a vision processor to identify, classify, and track objects for vision-based driver assistance and related vision-based assistance actions.

Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.

Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.

Abstract: An electronic device is described that includes: a host processor comprising at least one input port configured to receive a plurality of data signals on a plurality of virtual channels; and a memory operably coupled to the host processor and configured to receive and store data. The host processor is configured to enable and disable individual virtual channels from the plurality of virtual channels and is configured to only store data in memory associated with enabled virtual channels, and discard data from disabled channels.

Abstract: A video device is described that includes: a host processor comprising at least one input video port configured to receive a plurality of video data signals that comprise video data and embedded data from a plurality of virtual channels in a received frame; and a memory operably coupled to the host processor and configured to receive and store video data. The host processor is configured to segregate the video data from the embedded data in the received frame and process the embedded data individually.

Abstract: In the case of a component which conducts high-pressure medium, comprising a first component (13) with at least one pressure duct (29) and a second component (2) with a pressure chamber (30), wherein an annular sealing surface (32), which surrounds the mouth(s) of the at least one pressure duct (29), of the first component (13) and an annular sealing surface (33), which surrounds the rim of the pressure chamber (30), of the second component (2) interact areally with one another to form a sealing point, wherein the cross-sectional area of the pressure duct (29) is smaller than the cross-sectional area of the pressure chamber (30), the pressure-induced radial expansion of the annular sealing surfaces (32, 33) is substantially equal.

Abstract: The invention relates to novel compounds of formula I where R1, R2, R3, R4, R5, R6, R7, R8, Q1, Q2 and Q3 are each as defined below. The compounds of formula I have antithrombotic activity and inhibit especially protease-activated receptor 1 (PAR1). The invention further relates to a process for preparing the compound of formula I and to the use thereof as a medicament.

Abstract: A MEMS structure includes a backplate, a membrane, and an adjustable ventilation opening configured to reduce a pressure difference between a first space contacting the membrane and a second space contacting an opposite side of the membrane. The adjustable ventilation opening is passively actuated as a function of the pressure difference between the first space and the second space.

Abstract: This disclosure relates to compounds of formula I: wherein R1, R2, R3, R4, X and Y have the meanings denoted in the disclosure. The compounds of formula I have antithrombotic activity and in particular inhibit the protease-activated receptor 1 (PAR1). The disclosure further relates to a method for producing the compound of formula I and to the use thereof as a pharmaceutical product.

Abstract: The invention relates to novel compounds of formula I where X, A?, Q1, Q2, Q3, R2, R3, R4, R5, R6, R7, R8 and R9 are each as defined below. The compounds of formula I have antithrombotic activity and inhibit especially protease-activated receptor 1 (PAR1). The invention further relates to a process for preparing the compound of formula I and to the use thereof as a medicament.

Abstract: The disclosure relates to compounds of formula I: wherein the groups R1, R2, R3, R4, R5 and X are as defined in the disclosure, having antithrombotic activity, which in particular inhibits the protease-activated receptor 1 (PAR1). The disclosure further relates to methods for producing the same and to the use thereof as a pharmaceutical product.