Abstract: In a circuit for suppressing short-lived noise phenomena in a digital audio signal, in particular during a temporary test reception of another transmitter, the audio signal is multiplied by a factor which, prior to the appearance of the noise phenomenon, is brought from a maximum value to a minimum value in accordance with a predetermined time function, and at the end of the noise phenomenon, is returned to a maximum value. The invention has special application to the Radio Data System defined by the European Broadcasting Union, and the testing of "Alternative Frequencies" in that system.

Abstract: In a radio receiver with digital signal processing, a stereo multiplex signal received and the useful signals derived therefrom are processed in digital form at a first sampling rate. The subsidiary signals derived from the stereo multiplex signal are at least partly processed at a second sampling rate that is smaller than the first sampling rate. The sampling rate of the processed subsidiary signals are reduced to the first sampling rate with the processed subsidiary signals, acting as control signals with the first sampling rate, affecting the stereo multiplex signal and the useful signals.

Abstract: In a circuit arrangement for deriving a signal dependent on the change direction of the incoming signal level in a radio receiver, controllable by a microcomputer, a comparator is provided outside the microcomputer to which a signal representing the respective signal strength and a signal generated by the microcomputer representing the signal strength at an earlier point in time can be supplied. An output signal from the comparator can be supplied to the microcomputer.

Abstract: Radio receivers which scan through a predetermined band of the radio spectrum, in a station-seeking mode, must independently detect whether the currently tuned frequency is the central frequency of the transmitting station and whether this transmitter provides a signal whose strength is sufficient, i.e. whose strength exceeds a predetermined threshold value. Once these two conditions are satisfied, the radio generates a "stop" signal which terminates the station-seeking mode, i.e. keeps the tuning circuit set to the frequency which provided the sufficiently strong signal. The present invention provides an unusually simple way to determine whether these two conditions are satisfied, by using a Finite-Impulse-Response digital filter (2) to extract a d.c. component of the demodulated signal (MPX), for comparison (6) with a predetermined maximum value, and by filtering (10) a field strength signal (FST), for comparison (11) with a predetermined minimum value.

Abstract: In a circuit for digital processing of audio signals in a radio receiver, preferably in a car radio, the audio signals pass through a digital filter designed as a tone control, whose frequency response can be controlled with supplied coefficients, and a volume control, whose transmission factor can be controlled with supplied control signals. If the high and/or low frequencies are raised, the transmission factor of the filter at medium frequencies can be correspondingly lowered. Volume control compensates for the reduction. The volume control may contain a digital and an analog portion.

Abstract: A digital circuit arrangement for transforming an input digital picture signal onto a reference horizontal synchronizing signal raster derived from the system clock, which input digital picture signal is present at a system clock rate not locked with the input digital picture signal, which includes a correction memory (1), an interpolator/decimator (2), and a control member for the purpose of a transformation which is as insensitive to interference as possible.

Abstract: A circuit arrangement for converting a digital signal of a first frequency into a signal of a second frequency and including an interpolator/decimator is characterized, notably for asynchronous first and second clock signals, in that there is provided at least one multiplexer arrangement which includes a first register which is clocked at the inverted first clock frequency and a second register which is clocked at the second clock frequency, and also includes a multiplexer, the input signal of the multiplexer arrangement being applied to the first register and to a first input of the multiplexer whose second input is coupled to the output of the first register, there also being provided a control circuit which alternately switches the signals applied to the two inputs of the multiplexer to its output in such a manner that at the instants at which this signal is written into the second register a valid signal is always present at the output of the multiplexer.

Abstract: In a digital circuit arrangement for processing an analog video signal, which operates at a fixed system clock not coupled to the video signal, in which the video signal is sampled and which comprises a correction memory (4) and an interpolator with decimator (14) which are used for converting the digital video signal to a synchronizing signal raster predetermined by the system clock, there is provided that the correction memory (4) has a predetermined number of memory sections (5, 6, 7, 8) arranged for storing each the sample values of one picture line which sample values are written or read out at the system clock, that each horizontal synchronizing pulse of the still unconverted video signal triggers a writing process of the subsequent picture line into a memory section (5, 6, 7, 8) and that each horizontal synchronizing pulse derived from the system clock triggers a reading process of the picture line that follows the previously read picture line.