Patents by Inventor Matthias Hierlemann

Matthias Hierlemann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory cell, wafer, semiconductor component with memory cell having insulation collars and method for fabricating an insulating collar for a memory cell
    Patent number: 6876026
    Abstract: The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.
    Type: Grant
    Filed: October 22, 2002
    Date of Patent: April 5, 2005
    Assignee: Infineon Technologies AG
    Inventors: Matthias Hierlemann, Rudolf Strasser
  • Method and apparatus of stress relief in semiconductor structures
    Publication number: 20040227214
    Abstract: A method, apparatus and system are provided for relieving stress in the via structures of semiconductor structures whenever a linewidth below a via is larger than a ground-rule, including providing a via at least as large as the groundrule, providing a landing pad above the via, providing a via bar in place of a via, slotting the metal linewidth below the via, or providing an oversize via with a sidewall spacer.
    Type: Application
    Filed: May 16, 2003
    Publication date: November 18, 2004
    Inventors: Mark Hoinkis, Matthias Hierlemann, Gerald Friese, Andy Cowley, Dennis J. Warner, Erdem Kaltalioglu
  • Memory cell, wafer, semiconductor component with memory cell and a method for fabricating an insulating collar for a memory
    Publication number: 20030077873
    Abstract: The invention relates to a DRAM memory cell having a trench filled with conductive material connected to a selection transistor by a connection having a vertical insulation collar arranged perpendicularly to a layer sequence of the memory cell. The vertical insulation collar is connected to a lateral insulation collar of the trench. This lateral insulation collar essentially extends perpendicular to the vertical insulation collar or is arranged laterally with respect to the vertical insulation collar. It is thus possible to provide a memory cell, a wafer and a semiconductor component that have a high integration density and a sufficient dielectric strength, and that efficiently suppress parasitic transistors. A method for fabricating a lateral insulating collar for a memory cell is also described.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 24, 2003
    Inventors: Matthias Hierlemann, Rudolf Strasser