Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

Abstract: A computer-implemented method for instrumentation-assisted debugging is provided. The computer-implemented method includes compiling a hardware design to generate a compiled design, generating, from the compiled design, code for the hardware design and debug assist elements, feeding the code into a vendor emulation flow that outputs a vendor waveform and transforming the vendor waveform into a logic simulation waveform that is compatible with a hardware design language (HDL) using the debug assist elements for hardware logic debugging.

Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.

Abstract: Combining PCIe partial store commands along cache line boundaries, including: receiving a plurality of Peripheral Component Interface express (PCIe) packets; splitting the plurality of PCIe packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.

Abstract: A set control composition for cementitious systems comprises a) (a-1) a hydroxy monocarboxylic acid or a salt thereof, and (a-2) optionally, a polycarboxylic acid having a carboxylic acid equivalent weight of 333 or less, or a salt thereof, the carboxylic acid equivalent weight being the molecular weight of the polycarboxylic acid divided by the number of carboxylic acid functional groups, wherein (a-1) contributes at least 90% of the carboxyl groups to the total number of carboxyl groups of (a-1) and (a-2), b) at least one of (b-1) a borate source, and (b-2) a carbonate source, wherein the carbonate source is selected from inorganic carbonates having an aqueous solubility of 0.1 g·L?1 or more at 25° C., and organic carbonates, in a weight ratio of b) to a) in the range of 1.2 to 20, and c) a polyol in a weight ratio of c) to a) in the range of 1.0 to 10.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: A network of hang avoidance controllers and components which provide layer or scope based hang avoidance mechanisms in a distributed computing system is described. The detection of hang avoidance conditions and activation of the hang avoidance mechanisms are implemented on various limited scopes in the computing system, which prevent unnecessary system wide interruptions to avoid potential hangs in the system.

Abstract: A data processing system includes a system fabric coupling a coherence manager and an input/output (I/O) requestor. The I/O requestor issues a first snoop request of a first I/O store operation and a subsequent second snoop request of a second I/O store operation. Each of the first and second snoop requests specifies an update to a respective storage location identified by a coherent memory address. The I/O requestor receives respective ownership coherence responses for each of the first and second I/O store operations. The respective first and second ownership coherence responses indicate the coherence manager has concurrent coherence ownership of the memory address for both the first and second I/O store operations. In response to receipt of each of the ownership coherence responses, the I/O requestor issues respective first and second execute coherence responses to command the coherence manager to initiate updates to the respective storage locations.

Abstract: Combining PCIe partial store commands along cache line boundaries, including: receiving a plurality of Peripheral Component Interface express (PCIe) packets; splitting the plurality of PCIe packets along cache line boundaries to generate a plurality of partial store commands; and combining one or more sets of partial store commands to generate one or more combined partial store commands aligned to the cache line boundaries.

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Abstract: Embodiments are for preemptive tracking of remote requests for decentralized hot cache line fairness tracking. Authority is requested for a cache line in conjunction with querying for outstanding requests for the cache line. One or more responses are received regarding the outstanding requests for the cache line. In response to receiving the one or more responses regarding the outstanding requests and in advance of receiving the authority for the cache line, the outstanding requests are preemptively tracked in a requested structure associated with the cache line.

Abstract: Embodiments include processing commands on multiprocessor chip having a plurality of nodes that are interconnected via a clockwise ring network and a counterclockwise ring network. Aspects include receiving a command for execution and based at least in part on a determination that the clockwise ring network and the counterclockwise ring network are both available for transmission, performing a bidirectional execution of the command. The bidirectional execution includes transmitting a first warning signal on the clockwise ring network and a second warning signal on the counterclockwise ring network, transmitting the command on the clockwise ring network a first number of clock cycles after the first warning signal, and transmitting the command on the counterclockwise ring network a second number of clock cycles after the second warning signal.

Abstract: Embodiments are for using a decentralized hot cache line tracking fairness mechanism. In response to receiving an incoming request to access a cache line, a determination is made to grant access to the cache line based on a requested state and a serviced state used for maintaining the cache line, a structure comprising the requested and serviced states. In response to the determination to grant access to the cache line, the requested state and the serviced state are transferred along with data of the cache line.

Abstract: A construction composition comprises a) a cementitious binder comprising one or more calcium silicate mineral phases and one or more calcium aluminate mineral phases; b) optionally, an extraneous aluminate source; c) a sulfate source; d) an ettringite formation controller comprising (i) glyoxylic acid, a glyoxylic acid salt and/or a glyoxylic acid derivative; and (ii) at least one of a borate source and a carbonate source, wherein the carbonate source is selected from inorganic carbonates having an aqueous solubility of 0.1 g·L?1 or more, organic carbonates, and mixtures thereof; and e) a polyol in an amount of 0.2 to 2.5 wt.-%, relative to the amount of cementitious binder a). The composition contains 0.05 to 0.2 mol of total available aluminate, calculated as Al(OH)4?, from the calcium aluminate mineral phases plus the optional extraneous aluminate source, per 100 g of cementitious binder a); and the molar ratio of total available aluminate to sulfate is 0.4 to 2.0.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.

Abstract: An interrupt signal is provided to a guest operating system. A bus connected module is operationally connected with a plurality of processors via a bus attachment device. The bus attachment device receives an interrupt signal from the bus connected module with an interrupt target ID identifying one of the processors assigned for use by the guest operating system as a target processor for handling the interrupt signal. The bus attachment device checks whether the target processor is running using a running indicator provided by an interrupt table entry stored in a memory operationally connected with the bus attachment device. If the target processor is running, the bus attachment device forwards the interrupt signal to the target processor for handling. A translation of the interrupt target ID to a logical processor ID of the target processor is used to address the target processor directly.

Abstract: A method, programming product, and/or system is disclosed for identifying flaws in integrated circuits, e.g., processors, that includes: selecting from a list of a plurality of timing issues in an integrated circuit, where each timing issue on the list is represented by one or more VHDL code lines, a particular timing issue to investigate; tracing back the selected one or more VHDL code lines, corresponding to the selected particular timing issue to investigate, to one or more selected physical design VHDL (PD-VHDL) code lines; logically navigating across the one or more selected PD-VHDL code lines to one or more corresponding normalized VHDL (NVDHL) code lines; and tracing back the one or more corresponding NHVDL code lines to one or more short-hand VHDL (SVHDL) code lines to identify one or more code lines, written by a code designer, responsible for the particular timing issue being investigated.

Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.

Abstract: An input/output store instruction is handled. A data processing system includes a system nest communicatively coupled to at least one input/output bus by an input/output bus controller. The data processing system further includes at least a data processing unit including a core, system firmware and an asynchronous core-nest interface. The data processing unit is communicatively coupled to the system nest via an aggregation buffer. The system nest is configured to asynchronously load from and/or store data to an external device which is communicatively coupled to the input/output bus. The data processing unit is configured to complete the input/output store instruction before an execution of the input/output store instruction in the system nest is completed.