Patents by Inventor Matthias Klein

Matthias Klein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10985778
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Grant
    Filed: January 14, 2020
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Patent number: 10983833
    Abstract: An aspect includes hardware accelerator access. An application executing on a core of a multi-core processor triggers an interface code routine to acquire ownership of a hardware accelerator that is shared by a plurality of cores. The interface code routine partitions an input work package of the application into a plurality of pages in one or more input queues. The input work package is provided to the hardware accelerator in groups of one or more pages through the one or more input queues based on acquiring ownership of the hardware accelerator.
    Type: Grant
    Filed: July 31, 2019
    Date of Patent: April 20, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Brenton F. Belmar, Christian Jacobi, Matthias Klein, Peter G. Sutton
  • Publication number: 20210111082
    Abstract: A packaged electronic die having a micro-cavity and a method for forming a packaged electronic die. The packaged electronic die includes a photoresist frame secured to the electronic die and extending completely around the device. The photoresist frame is further secured to a first major surface of a substrate so as to form an enclosure around the device. Encapsulant material extends over the electronic die and around the sides of the electronic die. The encapsulant material is in contact with the first major surface of the substrate around the entire periphery of the electronic die so as to form a seal around the electronic die.
    Type: Application
    Filed: March 11, 2020
    Publication date: April 15, 2021
    Applicant: Microchip Technology Inc.
    Inventors: Matthias Klein, Andreas Zakrzewski, Richard Gruenwald
  • Patent number: 10949097
    Abstract: A set of memory access operations is obtained. The set of memory access operations includes a plurality of memory access operations to be chained, in which the plurality of memory access operations are to be processed as an atomic unit. The plurality of memory access operations are executed in a particular order, and one or more results are provided.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: March 16, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Edward W. Chencinski, Bruce Ratcliff, Eric N. Lais, Michael James Becht, Matthias Klein
  • Patent number: 10944423
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Grant
    Filed: March 14, 2019
    Date of Patent: March 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Timothy Siegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup
  • Publication number: 20210064504
    Abstract: Identifying computer program execution characteristics for determine relevance of pattern instruction executions to determine characteristics of a computer program. Filters are utilized to determine which subsequent occurrences of execution of at least one computer instruction are relevant to a counter based on execution characteristics of the at least one computer instruction where the counter counts the subsequent occurrences of execution of at least one computer instruction following prior executions of the same at least one computer instruction.
    Type: Application
    Filed: September 4, 2019
    Publication date: March 4, 2021
    Inventors: Anthony Thomas Sofia, Peter Sutton, Robert W. St. John, Matthias Klein
  • Publication number: 20210064440
    Abstract: A processor requests that a data transformation operation be performed using another processor, in which the data transformation operation is performed asynchronously. A determination is made that the data transformation operation performed using the other processor has completed unsatisfactorily, and based on the unsatisfactory completion, status relating to performance of the data transformation operation is incomplete. The data transformation operation is then re-executed synchronously using the one processor, and the re-executing provides status information unavailable in performing the data transformation operation asynchronously.
    Type: Application
    Filed: August 26, 2019
    Publication date: March 4, 2021
    Inventors: Matthias Klein, Timothy Slegel, Anthony T. Sofia, Simon Weishaupt, Bruce C. Giamei, Louis P. Gomes, Mahmoud Amin
  • Patent number: 10936283
    Abstract: A logic device includes a compare unit at one level of a plurality of levels of a hierarchical structure to be used in sorting of records. The compare unit includes a buffer pair in which one or more buffers of the buffer pair are adapted to store at least one record. The logic device further includes another compare unit on another level of the plurality of levels of the hierarchical structure. The other compare unit includes another buffer pair in which one or more other buffers of the other buffer pair are adapted to store a portion of a record. A size of the one or more other buffers of the other buffer pair is insufficient to store the entire record. The one compare unit and the other compare unit are adapted to sort a plurality of records.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Norbert Hagspiel, Jörg-Stephan Vogt, Christian Jacobi, Matthias Klein
  • Patent number: 10936517
    Abstract: A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.
    Type: Grant
    Filed: June 25, 2019
    Date of Patent: March 2, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Norbert Hagspiel, Sascha Junghans, Matthias Klein, Joerg Walter
  • Patent number: 10915461
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for cache eviction. The method includes detecting a first data in a shared cache and a first cache in response to a request by a first processor. The first data is determined to have a mid-level cache eviction priority. A request is detected from a second processor for a same first data as requested by the first processor. However, in this instance, the second processor has indicated that the same first data has a low-level cache eviction priority. The first data is duplicated and loaded to a second cache, however, the data has a low-level cache eviction priority at the second cache.
    Type: Grant
    Filed: March 5, 2019
    Date of Patent: February 9, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ekaterina M. Ambroladze, Robert J. Sonnelitter, III, Matthias Klein, Craig Walters, Kevin Lopes, Michael A. Blake, Tim Bronson, Kenneth Klapproth, Vesselina Papazova, Hieu T Huynh
  • Publication number: 20210034438
    Abstract: Embodiments of the present invention are directed to a computer-implemented method for controller address contention assumption. A non-limiting example computer-implemented method includes a shared controller receiving a fetch request for data from a first requesting agent, the receiving via at least one intermediary controller. The shared controller performs an address compare using a memory address of the data. In response to the memory address matching a memory address stored in the shared controller, the shared controller acknowledges the at least one intermediary controller's fetch request, wherein upon acknowledgement, the at least one intermediary controller resets. In response to release of the data by a second requesting agent, the shared controller transmits the data to the first requesting agent.
    Type: Application
    Filed: July 31, 2019
    Publication date: February 4, 2021
    Inventors: Robert J. Sonnelitter, III, Michael Fee, Craig R. Walters, Arthur O'Neill, Matthias Klein
  • Patent number: 10896022
    Abstract: A compare unit includes an array including a plurality of buffer pairs to receive records on one level of a plurality of levels of a hierarchical structure. A comparator is coupled to the array, and the comparator includes one input to receive one beat of one record from one buffer of a selected buffer pair of the plurality of buffer pairs coupled to the comparator. The comparator further includes another input to receive another beat of another record from another buffer of the selected buffer pair, and logic coupled to the one input and the other input to compare the one beat and the other beat to obtain a winner beat of the compare.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 19, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jörg-Stephan Vogt, Norbert Hagspiel, Christian Jacobi, Matthias Klein
  • Publication number: 20200379760
    Abstract: In one example implementation according to aspects of the present disclosure, a computer-implemented method for executing a load instruction with a timeout includes receiving, by a processing device, the load instruction. The method further includes attempting, by the processing device, to load a lock on a cache line of a memory. The method further includes determining, by the processing device, whether the timeout has expired prior to a successful loading of the lock on the cache line. The method further includes , responsive to determining that the timeout has expired, executing, by the processing device, another instruction instead of loading the lock on the cache line.
    Type: Application
    Filed: May 28, 2019
    Publication date: December 3, 2020
    Inventors: Christian Jacobi, Matthias Klein, Martin Recktenwald, Anthony Saporito, Robert J. Sonnelitter, III
  • Publication number: 20200356485
    Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, wherein a cached data item is assigned to a first core of the processor cores for exclusively executing an atomic primitive by the first core. The method comprises, while the execution of the atomic primitive is not completed by the first core, receiving from a second core at a cache controller a request for accessing the data item. In response to determining that a second request of the data item is received from a third core, of the plurality of processor cores, before receiving the request of the second core, a rejection message may be returned to the second core.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventors: Ralf Winkelmann, Michael Fee, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger
  • Publication number: 20200356418
    Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores including a first processor core and a second processor core, wherein a data item is exclusively assigned to the first processor core, of the plurality of processor cores, for executing an atomic primitive by the first processor core. The method includes receiving by the first processor core, from the second processor core, a request for accessing the data item, and in response to determining by the first processor core that the executing of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventors: Ralf Winkelmann, Michael Fee, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger
  • Publication number: 20200356420
    Abstract: The present disclosure relates to a method for a computer system comprising a plurality of processor cores, including a first processor core and a second processor core, wherein a cached data item is assigned to a first processor core, of the plurality of processor cores, for exclusively executing an atomic primitive. The method includes receiving, from a second processor core at a cache controller, a request for accessing the data item, and in response to determining that the execution of the atomic primitive is not completed by the first processor core, returning a rejection message to the second processor core.
    Type: Application
    Filed: May 9, 2019
    Publication date: November 12, 2020
    Inventors: Ralf Winkelmann, Michael Fee, Matthias Klein, Carsten Otte, Edward W. Chencinski, Hanno Eichelberger
  • Patent number: 10831497
    Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell, Timothy Slegel, Ashutosh Mishra, Christian Jacobi
  • Publication number: 20200321976
    Abstract: Compressing data includes hashing a first token length of an incoming data steam into a hash table, where the first token length includes a plurality of bytes. A second token length of the incoming data stream may be hashed into the hash table. The second token may be larger than the first token length and includes the plurality of bytes. The method may further include automatically comparing which token length enabled more efficient data compression, and automatically adjusting at least one of the first and second token lengths based on the comparison.
    Type: Application
    Filed: April 2, 2019
    Publication date: October 8, 2020
    Inventors: Bulent ABALI, Ashutosh MISRA, Girish G. KURUP, Deepankar BHATTACHARJEE, Matthias KLEIN
  • Publication number: 20200301604
    Abstract: Various embodiments are provided for managing multiport banked memory arrays in a computing system by a processor. One or more conflicts may be eliminated in a multiport banked memory array upon receiving one or more write operations, read operations, or a combination thereof according to a selected priority and access protocol.
    Type: Application
    Filed: March 19, 2019
    Publication date: September 24, 2020
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bulent ABALI, Ashutosh Misra, Hubertus FRANKE, Matthias KLEIN, Deepankar Bhattacharjee, Girish Kurup
  • Publication number: 20200293377
    Abstract: Embodiments of the invention are directed to a DEFLATE compression accelerator and to a method for verifying the correctness of the DEFLATE compression accelerator. The accelerator includes an input buffer and a Lempel-Ziv 77 (LZ77) compressor communicatively coupled to an output of the input buffer. A switch is communicatively coupled to the output of the input buffer and to the output of the LZ77 compressor. The switch is configured to bypass the LZ77 compressor during a compression test. The accelerator further includes a deflate Huffman encoder communicatively coupled to an output of the switch and an output buffer communicatively coupled to the deflate Huffman encoder. When the switch is not bypassed, the compressor can be modified to produce repeatable results.
    Type: Application
    Filed: January 14, 2020
    Publication date: September 17, 2020
    Inventors: Timothy Slegel, Mark Farrell, Bruce Giamei, Matthias Klein, Ashutosh Misra, Simon Weishaupt, Girish Gopala Kurup