Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high resistivity region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high resistivity region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract: Cylindrical optical components of quartz glass are known, which have an inner zone made of an inner zone glass, which extends in the direction of the longitudinal axis and is surrounded by a jacket zone made of a jacket zone glass, the average pt wall thickness thereof varying at least over a part of its length in the direction of the longitudinal axis of the component. The aim of the invention is to provide a method that allows a simple and cost-effective production of such an optical component from quartz glass.

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: A power device with improved reliability and a method for producing the same is disclosed. One embodiment provides an active area having an electrical power dissipation characteristic, a metallization layer portion configured with respect to the active area so that the dissipation characteristic of the active area results in heating the metallization layer portion, the metallization layer portion being formed as a connected region. The metallization layer portion has at least one hole, fully extending through the metal layer and having a dielectric. The at least one hole is arranged so that each location of the metal layer portion is connected electrically to each other location via the metallization material of the metal layer portion.

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Abstract: A semiconductor device and manufacturing method is disclosed. One embodiment provides a common substrate of a first conductivity type and at least two wells of a second conductivity type. A buried high Ohmic region and at least an insulating structure is provided insulating the first well from the second well. The insulating structure extends through the buried high Ohmic region and includes a conductive plug in Ohmic contact with the first semiconductor region. A method for forming an integrated semiconductor device is also provided.

Abstract: A temperature sensor structure for a semiconductor device. One embodiment provides a semiconductor substrate including the semiconductor device. A dissipation region of the semiconductor device is adjacent to a main surface of the semiconductor substrate. A first layer arrangement is disposed on the main surface of the semiconductor substrate adjacent to the dissipation region of the semiconductor device. A second layer arrangement is disposed on the first layer arrangement with an insulation layer for galvanic separation therebetween. The first and second layer arrangements and the insulation layer form a layer structure on the main surface above the dissipation region. A circuit element is disposed in the second layer arrangement, the circuit element having a temperature-dependent characteristic and being coupled thermally to the dissipation region.

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.

Abstract: An integrated semiconductor with lateral thermal insulation is disclosed. In one embodiment, the chip has, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions. At least one thermally insulating trench is provided at least in each interspace in each case between power semiconductor circuit region(s) and temperature-sensitive semiconductor circuit region(s), which at least one thermally insulating trench extends into the depth of the chip right into the substrate and in the longitudinal direction of the chip at least over a lateral side of the at least one power semiconductor circuit region and/or the temperature-sensitive semiconductor circuit region and is either unfilled or filled with a thermally insulating filling material.

Abstract: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.

Abstract: A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer.

Abstract: An electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, and to a method for producing the connection arrangement is disclosed. In one embodiment, a metallic layer is deposited onto at least one contact terminal and/or the contacts and the wire, the metallic layer protecting the contact terminal or the electrical connection against ambient influences and ensuring a high reliability.