Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.

Abstract: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the side edges, the rear side and the top side, on which surface-mountable external contacts are arranged. One embodiment includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.

Abstract: A semiconductor emitter structure for emitting charge carriers of a first conductivity type in a base volume of a second conductivity type material neighbored to the emitter structure in a vertical direction, includes multiple emitter volumes of first conductivity tape material having a predetermined lateral dimension in a lateral direction perpendicular to the vertical direction. The emitter volumes are, in the lateral direction, neighbored by semiconductor volumes of second conductivity type material, wherein the predetermined lateral dimension is such that space charges created by second conductivity type carriers laterally diffusing into the emitter volumes from the semiconductor volumes limit a maximum density of first conductivity type carriers within the emitter volumes by more than 20% as compared to emitter volumes of the same lateral dimension not neighbored by semiconductor volumes of the second conductivity type material.

Abstract: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the edge sides and the rear side and partly covers the top side, on which surface-mountable external contacts are arranged. One aspect includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.

Abstract: An apparatus and a method configured to lower thermal stress is disclosed. One embodiment provides a semiconductor chip, a lead frame and a layer structure. The layer structure includes at least a diffusion solder layer and a buffer layer. The layer structure is arranged between the semiconductor chip and the lead frame. The buffer layer includes a material, which is soft in comparison to a material of the diffusion solder layer, and includes a layer thickness such that thermal stresses in the semiconductor chip remain below a predetermined value during temperature fluctuations within a temperature range.

Abstract: A semiconductor component having improved thermomechanical durability has in a semiconductor substrate at least one cell comprising a first main electrode zone, a second main electrode zone and a control electrode zone lying in between. For making contact with the main electrode zone, at least one metallization layer composed of copper or a copper alloy is provided which is connected to at least one bonding electrode which likewise comprises copper or a copper alloy.

Abstract: One or more embodiments are related to a semiconductor device, comprising: a metallization layer comprising a plurality of portions, each of the portions having a different thickness. The metallization layer may be a final metal layer.

Abstract: A semiconductor component has a semiconductor body and also a metal/insulation structure arranged above the semiconductor body and having a plurality of metal regions and insulation regions laterally adjoining one another. The metal regions serve for supplying the semiconductor body with electric current. Furthermore, the semiconductor component has a passivation layer arranged on the metal/insulation structure. The passivation layer includes a metal or a metal-containing compound.

Abstract: A semiconductor device is disclosed that improves heat dissipation by providing blind contact elements on a dielectric layer. Embodiments are disclosed which include a substrate having at least one electrode contact area accessible at a surface of the substrate and a surface adjacent the electrode contact area, a dielectric layer disposed above the surface; an intermediate oxide layer disposed above the dielectric layer, a current conducting metallization layer disposed above the intermediate oxide layer; and at least one contact element vertically extending from the dielectric layer through the intermediate oxide layer to the metallization layer above the surface adjacent the electrode contact area, the at least one contact element having a heat conductivity that is higher than that of the intermediate oxide layer.

Abstract: Emitter and collector regions of the bipolar transistor are formed by doped regions of the same type of conductivity, which are separated by doped semiconductor material of an opposite type of conductivity, the separate doped regions being arranged at a surface of a semiconductor body and being in electric contact with electrically conductive material that is introduced into trenches at the surface of the semiconductor body.

Abstract: A temperature sensor structure for a semiconductor device. One embodiment provides a semiconductor substrate including the semiconductor device. A dissipation region of the semiconductor device is adjacent to a main surface of the semiconductor substrate. A first layer arrangement is disposed on the main surface of the semiconductor substrate adjacent to the dissipation region of the semiconductor device. A second layer arrangement is disposed on the first layer arrangement with an insulation layer for galvanic separation therebetween. The first and second layer arrangements and the insulation layer form a layer structure on the main surface above the dissipation region. A circuit element is disposed in the second layer arrangement, the circuit element having a temperature-dependent characteristic and being coupled thermally to the dissipation region.

Abstract: A semiconductor device exhibits a first metal layer, made of a first metal, with at least one contiguous subsection. At least one second metal layer, made of a second metal, is placed on the contiguous subsection of the first metal layer. The second metal is harder than the first metal. The second metal layer is structured to form at least two layer regions, which are disposed on the contiguous subsection of the first metal layer. The second metal exhibits a boron-containing or phosphorus-containing metal or a boron-containing or phosphorus-containing metal alloy.

Abstract: An electronic device and method for production is disclosed. One embodiment provides an integrated component having a first layer which is composed of copper or a copper alloy or which contains copper or a copper alloy, and having an electrically conductive second layer, whose material differs from the material of the first layer, and a connection apparatus which is arranged on the first layer and on the second layer.

Abstract: A semiconductor component of semiconductor chip size includes a semiconductor chip. The semiconductor chip has a metallic coating that completely covers the edge sides and the rear side and partly covers the top side, on which surface-mountable external contacts are arranged. One aspect includes power semiconductor components, wherein the metallic coating connects a rear side electrode to one of the surface-mountable external contacts on the top side of a power semiconductor chip.

Abstract: An integrated semiconductor with lateral thermal insulation is disclosed. In one embodiment, the chip has, on a common substrate, at least one power semiconductor circuit region and, laterally adjacent to the power semiconductor circuit region, at least one further temperature-sensitive semiconductor circuit region, interspaces being maintained between the circuit regions. At least one thermally insulating trench is provided at least in each interspace in each case between power semiconductor circuit region(s) and temperature-sensitive semiconductor circuit region(s), which at least one thermally insulating trench extends into the depth of the chip right into the substrate and in the longitudinal direction of the chip at least over a lateral side of the at least one power semiconductor circuit region and/or the temperature-sensitive semiconductor circuit region and is either unfilled or filled with a thermally insulating filling material.

Abstract: A connection structure includes a semiconductor die having a first major surface and an electrically conductive substrate having a second major surface. At least part of the second major surface is positioned facing towards and spaced at a distance from the first major surface. A galvanically deposited metallic layer extends between the first major surface and the second major surface and electrically connects the first major surface and the second major surface.

Abstract: A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.

Abstract: Semiconductor components having a semiconductor body which includes a semiconductor base surface have to be sealed with a molding compound in order to protect against moisture or heat. Mechanical interlocking of the molding compound to the semiconductor base surface is achieved by means of at least one interlocking structure. This may be either a horizontal interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is horizontal with respect to the semiconductor base surface and/or a vertical interlocking structure for mechanically interlocking the molding compound to the semiconductor base surface in the direction which is vertical with respect to the semiconductor base surface.

Abstract: An integrated circuit and a production method is disclosed. One embodiment forms reverse-current complexes in a semiconductor well, so that the charge carriers, forming a damaging reverse current, cannot flow into the substrate.