Patents by Inventor Matty Caymax
Matty Caymax has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220277953Abstract: A method for providing a film of one or more monolayers of transition metal dichalcogenides on a substrate is disclosed. The method includes providing a substrate; depositing at least one monolayer of the transition metal dichalcogenides on the substrate; and selectively removing superficial islands on top of the at least one monolayer by thermal etching.Type: ApplicationFiled: February 22, 2022Publication date: September 1, 2022Inventors: Yuanyuan Shi, Benjamin Groven, Matty Caymax
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Patent number: 9984874Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.Type: GrantFiled: December 18, 2014Date of Patent: May 29, 2018Assignees: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Matty Caymax, Markus Heyne, Annelies Delabie
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Publication number: 20170250075Abstract: Method of producing one or more transition metal dichalcogenide (MX2) layers on a substrate, comprising the steps of: obtaining a substrate having a surface and depositing MX2 on the surface using ALD deposition, starting from a metal halide precursor and a chalcogen source (H2X), at a deposition temperature of about 300° C. Suitable metals are Mo and W, suitable chalcogenides are S, Se and Te. The substrate may be (111) oriented. Also mixtures of two or more MX2 layers of different compositions can be deposited on the substrate, by repeating at least some of the steps of the method.Type: ApplicationFiled: December 18, 2014Publication date: August 31, 2017Applicants: IMEC VZW, Katholieke Universiteit Leuven, KU LEUVEN R&DInventors: Matty Caymax, Markus Heyne, Annelies Delabie
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Publication number: 20170121814Abstract: The disclosure relates to an apparatus and method for delivering a precursor to a reaction chamber. One example embodiment is an apparatus for delivering a precursor to a reaction chamber. The apparatus includes a recipient configured to hold a quantity of the precursor in a solid or liquid state at a given temperature and pressure so as to vaporize the precursor. The apparatus also includes a carrier gas supply line, configured to supply a carrier gas to the recipient. Further, the apparatus includes a gas mixture transport line configured to transport a mixture of the carrier gas and a vapor of the precursor out of the recipient. The glass mixture transport line extends between the recipient and an outlet section of the gas mixture transport line.Type: ApplicationFiled: October 26, 2016Publication date: May 4, 2017Applicant: IMEC VZWInventor: Matty Caymax
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Patent number: 9431519Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.Type: GrantFiled: May 22, 2015Date of Patent: August 30, 2016Assignees: IMEC VZW, Sony CorporationInventors: Hideki Minari, Shinichi Yoshida, Geoffrey Pourtois, Matty Caymax, Eddy Simoen
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Patent number: 9425314Abstract: A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h?, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.Type: GrantFiled: March 5, 2014Date of Patent: August 23, 2016Assignee: IMECInventors: Clement Merckling, Matty Caymax
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Patent number: 9218964Abstract: Methods of manufacturing a III-V compound semiconductor material, and the semiconductor material thus manufactured, are disclosed. In one embodiment, the method comprises providing a substrate comprising a first semiconductor material having a {001} orientation and an insulating layer overlaying the first semiconductor material. The insulating layer comprises a recessed region exposing an exposed region of the first semiconductor material. The method further comprises forming a buffer layer overlaying the exposed region that comprises a group IV semiconductor material. The method further comprises thermally annealing the substrate and the buffer layer, thereby roughening the buffer layer to create a rounded, double-stepped surface having a step density and a step height. A product of the step density and the step height is greater than or equal to 0.05 on the surface.Type: GrantFiled: August 5, 2011Date of Patent: December 22, 2015Assignees: IMEC, Katholieke Universiteit Leuven, KU Leuven R&DInventors: Gang Wang, Matty Caymax, Maarten Leys, Wei-e Wang, Niamh Waldron
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Publication number: 20150340503Abstract: A method of producing a III-V fin structure within a gap separating shallow trench isolation (STI) structures and exposing a semiconductor substrate is disclosed, the method comprising providing a semiconductor substrate, providing in the semiconductor substrate at least two identical STI structures separated by a gap exposing the semiconductor substrate, wherein said gap is bounded by said at least two identical STI structures, and, producing a III-V fin structure within said gap on the exposed semiconductor substrate, and providing a diffusion barrier at least in contact with each side wall of said at least two identical STI structures and with side walls of said III-V fin structure and wherein said semiconductor substrate is a Si substrate.Type: ApplicationFiled: May 22, 2015Publication date: November 26, 2015Applicants: SONY CORPORATION, IMEC VZWInventors: Hideki Minari, Shinichi Yoshida, Geoffrey Pourtois, Matty Caymax, Eddy Simoen
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Patent number: 9196477Abstract: A semiconductor device and a method of manufacturing the device is disclosed. In one aspect, a method includes providing a substrate, providing a first epitaxial semiconducting layer on top of the substrate, and forming a one- or two-dimensional repetitive pattern, each part of the pattern having an aspect ratio in the range of about 0.1 to 50.Type: GrantFiled: April 3, 2012Date of Patent: November 24, 2015Assignee: IMECInventors: Kai Cheng, Matty Caymax
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Patent number: 9028623Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.Type: GrantFiled: February 20, 2014Date of Patent: May 12, 2015Assignee: IMECInventors: Annelies Delabie, Matty Caymax
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Patent number: 8962369Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.Type: GrantFiled: July 10, 2013Date of Patent: February 24, 2015Assignee: IMECInventors: Roger Loo, Frederik Leys, Matty Caymax
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Patent number: 8912055Abstract: Disclosed are methods for forming hybrid metal-oxide-semiconductor field effect transistors (MOSFETs) and the hybrid MOSFETS thus obtained. In one embodiment, a method is disclosed that includes providing a first substrate comprising a first region and a second region, providing a second substrate comprising a second semiconductor layer and an insulating layer overlaying the second semiconductor layer, and direct substrate bonding the second substrate to the first substrate, thereby contacting the first region and the second region with the insulating layer. The method further includes selectively removing the second semiconductor layer and the insulating layer in the first region, thereby exposing the first semiconductor layer in the first region, forming a first gate stack of a first MOSFET on the exposed first semiconductor layer in the first region, and forming a second gate stack of a second MOSFET on the second semiconductor layer in the second region.Type: GrantFiled: May 2, 2012Date of Patent: December 16, 2014Assignee: IMECInventors: Thomas Y. Hoffman, Matty Caymax, Niamh Waldron, Geert Hellings
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Patent number: 8865582Abstract: Disclosed are methods for manufacturing floating gate memory devices and the floating gate memory devices thus manufactured. In one embodiment, the method comprises providing a monocrystalline semiconductor substrate, forming a tunnel oxide layer on the substrate, and depositing a protective layer on the tunnel oxide layer to form a stack of the tunnel oxide layer and the protective layer. The method further includes forming at least one opening in the stack, thereby exposing at least one portion of the substrate, and cleaning the at least one exposed portion with a cleaning liquid. The method still further includes loading the substrate comprising the stack into a reactor and, thereafter, performing an in-situ etch to remove the protective layer, using the at least one exposed portion as a source to epitaxially grow a layer comprising the monocrystalline semiconductor material, and forming the layer into at least one columnar floating gate structure.Type: GrantFiled: October 25, 2011Date of Patent: October 21, 2014Assignee: IMECInventors: Roger Loo, Matty Caymax, Pieter Blomme, Geert Van den Bosch
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Publication number: 20140252414Abstract: A semiconductor device includes a semiconductor substrate having a top surface, and at least one coated fin protruding perpendicularly from the surface and having a height h and side walls. The at least one coated fin further includes a core of one or more layers selected from the group consisting of (a) III-V compound layers and (b) a Ge layer, and a coating overlaying the core. The coating includes one or more metal oxide layers, at least one of which is aluminium. The device also includes a recess surrounding the at least one coated fin and being defined between two coated fins when more than one fin is present. The recess is filled up with a dielectric material so as to cover the coating on the side walls of the at least one fin up to a certain height h?, which is less than the height h. The present disclosure also relates to a method for producing the semiconductor device.Type: ApplicationFiled: March 5, 2014Publication date: September 11, 2014Applicant: IMECInventors: Clement Merckling, Matty Caymax
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Publication number: 20140239461Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.Type: ApplicationFiled: February 20, 2014Publication date: August 28, 2014Applicant: IMECInventors: Annelies Delabie, Matty Caymax
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Patent number: 8709918Abstract: A method for selective deposition of semiconductor materials in semiconductor processing is disclosed. In some embodiments, the method includes providing a patterned substrate comprising a first region and a second region, where the first region comprises an exposed first semiconductor material and the second region comprise an exposed insulator material. The method further includes selectively providing a film of the second semiconductor material on the first semiconductor material of the first region by providing a precursor of a second semiconductor material, a carrier gas that is not reactive with chlorine compounds, and tin-tetrachloride (SnCl4). The tin-tetrachloride inhibits the deposition of the second semiconductor material on the insulator material of the second region.Type: GrantFiled: January 17, 2012Date of Patent: April 29, 2014Assignee: IMECInventors: Benjamin Vincent, Roger Loo, Matty Caymax
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Publication number: 20140020619Abstract: Disclosed are methods for growing Sn-containing semiconductor materials. In some embodiments, an example method includes providing a substrate in a chemical vapor deposition (CVD) reactor, and providing a semiconductor material precursor, a Sn precursor, and a carrier gas in the CVD reactor. The method further includes epitaxially growing a Sn-containing semiconductor material on the substrate, where the Sn precursor comprises tin tetrachloride (SnCl4). The semiconductor material precursor may be, for example, digermane, trigermane, higher-order germanium precursors, or a combination thereof. Alternatively, the semiconductor material precursor may be a silicon precursor.Type: ApplicationFiled: March 29, 2012Publication date: January 23, 2014Inventors: Benjamin Vincent, Federica Gencarelli, Roger Loo, Matty Caymax
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Publication number: 20140008727Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.Type: ApplicationFiled: July 10, 2013Publication date: January 9, 2014Inventors: Roger Loo, Frederik Leys, Matty Caymax
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Patent number: 8530339Abstract: The present disclosure is related to a method for the deposition of a continuous layer of germanium on a substrate by chemical vapor deposition. According to the disclosure, a mixture of a non-reactive carrier gas and a higher order germanium precursor gas, i.e. of higher order than germane (GeH4), is applied. In an example embodiment, the deposition is done under application of a deposition temperature between 275° C. and 500° C., with the partial pressure of the precursor gas within the mixture being at least 20 mTorr for temperatures between 275° C. and 285° C., and at least 10 mTorr for temperatures between 285° and 500° C.Type: GrantFiled: January 11, 2012Date of Patent: September 10, 2013Assignee: IMECInventors: Benjamin Vincent, Matty Caymax, Roger Loo, Johan Dekoster
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Patent number: 8507337Abstract: A method for introducing species into a strained semiconductor layer comprising: providing a substrate comprising a first region comprising an exposed strained semiconductor layer, loading the substrate in a reaction chamber, then forming a conformal first species containing-layer by vapor phase deposition (VPD) at least on the exposed strained semiconductor layer, and thereafter performing a thermal treatment, thereby diffusing at least part of the first species from the first species-containing layer into the strained semiconductor layer and activating at least part of the diffused first species in the strained semiconductor layer.Type: GrantFiled: July 6, 2009Date of Patent: August 13, 2013Assignee: IMECInventors: Roger Loo, Frederik Leys, Matty Caymax