Patents by Inventor Mau-Chung Chang
Mau-Chung Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10852389Abstract: A frequency hopping continuous wave (FHCW) radar system which utilizes a one-coincidence sequence to create a form of FH multiplexing to allow discerning returning signals from interference. An EHC code generator sends codes to an FH waveform generator coupled to a transmitter. A receiver outputs a received signal to a correlator which correlates received signal with a delayed transmitted signal, and sends results for digital signal processing to determine target range and velocity. Use of the one-coincidence sequence provides for the interference level to be well managed and below the radar return signal; assuring that the returning radar signals can be discerned from interference.Type: GrantFiled: September 21, 2018Date of Patent: December 1, 2020Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Mau-Chung Chang, Yu-Hsiu Wu
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Patent number: 10707835Abstract: A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.Type: GrantFiled: December 26, 2018Date of Patent: July 7, 2020Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chia-Jen Liang, Yen-Cheng Kuan, Ching-Wen Chiang, Mau-Chung Chang
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Publication number: 20200195231Abstract: A wireless receiving device is provided. The wireless receiving device includes a first passive mixer and a common gate amplifier. The first passive mixer receives an oscillation signal. The common gate amplifier is coupled to the first passive mixer, and automatically adjusts the input impedance of the common gate amplifier according to the oscillation frequency of the oscillation signal.Type: ApplicationFiled: December 26, 2018Publication date: June 18, 2020Inventors: Chia-Jen LIANG, Yen-Cheng KUAN, Ching-Wen CHIANG, Mau-Chung CHANG
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Patent number: 10325047Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.Type: GrantFiled: October 1, 2015Date of Patent: June 18, 2019Assignee: Sage Software, Inc.Inventor: Mau-chung Chang
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Publication number: 20190094334Abstract: A frequency hopping continuous wave (FHCW) radar system which utilizes a one-coincidence sequence to create a form of FH multiplexing to allow discerning returning signals from interference. An EHC code generator sends codes to an FH waveform generator coupled to a transmitter. A receiver outputs a received signal to a correlator which correlates received signal with a delayed transmitted signal, and sends results for digital signal processing to determine target range and velocity. Use of the one-coincidence sequence provides for the interference level to be well managed and below the radar return signal; assuring that the returning radar signals can be discerned from interference.Type: ApplicationFiled: September 21, 2018Publication date: March 28, 2019Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Mau-Chung Chang, Yu-Hsiu Wu
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Patent number: 9898564Abstract: In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.Type: GrantFiled: January 7, 2015Date of Patent: February 20, 2018Assignee: Sage Software, Inc.Inventor: Mau-chung Chang
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Publication number: 20160197761Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.Type: ApplicationFiled: October 1, 2015Publication date: July 7, 2016Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Mau-Chung Chang, Sai-Wang Tam, Gyung-Su Byun, Yanghyo Kim, Kanit Therdsteerasukdi, Jeremy Ir, Glenn Reinman, Jingsheng Cong
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Publication number: 20160097795Abstract: In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.Type: ApplicationFiled: October 1, 2015Publication date: April 7, 2016Inventor: Mau-chung Chang
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Patent number: 9178725Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.Type: GrantFiled: August 12, 2013Date of Patent: November 3, 2015Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Mau-Chung Chang, Sai-Wang Tam, Gyung-Su Byun, Yanghyo Kim, Kanit Therdsteerasukdi, Jeremy Ir, Glenn Reinman, Jingsheng Cong
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Publication number: 20150199462Abstract: In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.Type: ApplicationFiled: January 7, 2015Publication date: July 16, 2015Inventor: Mau-chung Chang
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Patent number: 8832616Abstract: In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed.Type: GrantFiled: March 7, 2012Date of Patent: September 9, 2014Assignee: Sage Software, Inc.Inventor: Mau-chung Chang
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Publication number: 20140044157Abstract: Systems, apparatus, modules, and methods of communicating with memory devices utilizing multi-band communication containing a baseband and one or more amplitude shift keyed (ASK) RF channels over each differential pair of off-chip transmission lines. Configurations are described for interfacing between microprocessors, or controllers and memory devices or modules, and within a DIMM and its DRAM devices, and between multiple DIMM memory modules.Type: ApplicationFiled: August 12, 2013Publication date: February 13, 2014Applicant: THE REGENTS OF THE UNIVERSITY OF CALIFORNIAInventors: Mau-Chung Chang, Sai-Wang Tam, Gyung-Su Byun, Yanghyo Kim, Kanit Therdsteerasukdi, Jeremy Ir, Glenn Reinman, Jingsheng Cong
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Publication number: 20120240087Abstract: In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed.Type: ApplicationFiled: March 7, 2012Publication date: September 20, 2012Inventor: Mau-chung Chang
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Patent number: 8001502Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: August 16, 2011Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7992116Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: August 2, 2011Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7900175Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: March 1, 2011Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7895543Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: February 22, 2011Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7861201Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: December 28, 2010Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7650583Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: August 5, 2008Date of Patent: January 19, 2010Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang
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Patent number: 7590953Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.Type: GrantFiled: February 3, 2006Date of Patent: September 15, 2009Assignee: Sage Software, Inc.Inventor: Mau-Chung Chang