Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A fully alternating current (AC) coupled multi-point, multi-drop or point-to-point bus interconnect uses a low power synchronous pulsed signaling scheme for board-level chip-to-chip communication. A single-ended or differential pulsed signaling transceiver generates a diamond data eye with a small time constant in the pulsed signal. The transceiver includes a high-pass filter or a differentiator circuit network that generates triangle pulses that make the diamond data eye.

Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Abstract: A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g.

Abstract: A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.

Abstract: A system or method for controlling a voltage controlled oscillator (VCO) or LO buffer includes an amplitude detector for detecting an amplitude value at a node corresponding to the at least one output line. A comparator compares the detected amplitude value with a predetermined amplitude value, and outputs a first digital value when the detected amplitude value is greater than the predetermined amplitude value, and a second digital value when the detected amplitude value is less than the predetermined amplitude value. An accumulator accumulates outputs of the comparator so as to provide an accumulated digital amplitude value. A digital-to-analog converter converts the accumulated digital amplitude value to an accumulated analog amplitude value. The analog accumulated amplitude value is provided as an updated bias control signal to the bias transistor of the VCO or LO buffer.