Abstract: A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.

Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.

Abstract: A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.

Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.

Abstract: Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.

Abstract: An integrated circuit is provided with several superimposed levels of transistors, the circuit including an upper level provided with transistors having a rear gate electrode laid out on a first semiconducting layer, and a second semiconducting layer, a first transistor among the transistors of the upper level being provided with a contact pad traversing the second semiconducting layer, the contact pad being connected to a connection zone disposed between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line disposed on a side of a front face of the second semiconducting layer that is opposite to the rear face.

Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.

Abstract: Production of a 3D microelectronic device including: assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.

Abstract: Connection structure for microelectronic device with superposed semi-conductor layers comprising a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, said connection structure further comprising a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.

Abstract: An electronic component with multiple quantum islands is provided, including a substrate on which rests a nanowire made of semiconductor material not intentionally doped; two main control gates resting on the nanowire so as to form respective qubits in the nanowire, the two main control gates being separated by a groove, and bottom and lateral faces of the groove are covered by a dielectric layer; an element made of conductive material formed on the dielectric layer in the groove; a carrier reservoir that is offset with respect to the nanowire, the element made of the conductive material being separated from the carrier reservoir by another dielectric layer such that the element made of the conductive material is coupled to the carrier reservoir by field effect. A method of fabricating an electronic component with multiple quantum islands is also provided.

Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.

Abstract: A method of making a display device, the method including fabricating a matrix of light-emitting diodes (LEDs), each including electrodes accessible from a back face of the matrix and light-emitting surfaces accessible from a front face of the matrix; securing, onto the back face of the matrix, a stack of layers including at least one semiconducting layer, a gate dielectric layer, and a layer of gate conducting material; and starting from the stack of layers, fabricating an electronic control circuit electrically coupled to the electrodes, including fabricating field-effect transistors (FETs) including active zones and gates, the active zones being formed in the at least one semiconducting layer, and the gates being formed in the gate dielectric layer and in the layer of gate conducting material.

Abstract: Quantum device comprising: a quantum component forming a qubit, formed in an active layer of a substrate and comprising: a confinement region; charge carrier reservoirs; a first front gate covering the confinement region; first lateral spacers arranged around the first gate and covering access regions; an FET transistor formed in the active layer, comprising channel, source and drain regions formed in the active layer, a second front gate covering the channel region, and second lateral spacers arranged around the second front gate and covering source and drain extension regions; and wherein a width of the first lateral spacers is greater than that of the second lateral spacers.

Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.

Abstract: Integrated circuit provided with several superimposed levels of transistors including: an upper level provided with transistors with a rear gate electrode laid out on a first semiconducting layer and a second semiconducting layer, a first transistor among said transistors of said upper level being provided with a contact pad traversing the second semiconducting layer, said contact pad being connected to a connection zone arranged between the first semiconducting layer and the second semiconducting layer, the first transistor being polarised by and connected to at least one power supply line arranged on the side of a front face of the second semiconducting layer opposite to said rear face.

Abstract: A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.

Abstract: A quantum device with spin qubits, comprising: a first semiconducting layer comprising a first matrix of data qubits and measurement qubits connected to each other through tunnel barriers; means of addressing qubits configured for controlling conduction of each tunnel barrier by the field effect and comprising: first and second conducting portions arranged in first and second superposed metallisation levels respectively; first and second conducting vias each comprising a first end connected to one of the first and second conducting portions respectively, and a second end located facing one of the tunnel barriers; a first dielectric layer interposed between the tunnel barriers and the second ends of the first and second conducting vias.

Abstract: A method of making a display device comprising at least implementation of the following steps: fabricate a matrix of LEDs each comprising electrodes accessible from a back face of the LED matrix and light emitting surfaces on a front face of the LED matrix; securing a stack of layers comprising at least one semiconducting layer, a gate dielectric layer and a layer of gate conducting material, onto the back face of the LED matrix; starting from the stack of layers, fabricate an electronic control circuit electrically coupled to the electrodes of the LEDs, including the fabrication of FET transistors of which active zones are formed in the semiconducting layer and of which the gates are formed in the gate dielectric layer and in the layer of gate conducting material.

Abstract: The invention relates to a method for manufacturing a transistor comprising the preparation of a stack of layers of the semiconductor on insulator type comprising at least one substrate on which an insulating layer and an initial semiconductor layer are successively disposed. The method includes the formation of at least one oxide pad extending from a top face of the insulating layer, the formation of an additional layer made from semiconductor material covering the oxide pad and intended to form a channel for the transistor, the formation of a gate stack above the oxide pad, and the formation of a source and drain on either side of the gate stack.

Abstract: A method of fabrication of an integrated circuit is provided, including: providing a substrate including a first active layer and a first metallic level of interconnection arranged on top of the active layer and including first lines of interconnection separated by a first filling of sacrificial material; forming a superposition of an insulator layer and second lines of interconnection; providing access to the first filling through the insulator layer; filling the provided access with a second filling of sacrificial material; forming a second active layer on top of the second metallic level of interconnection; providing access to the second filling through the second active layer; and removing the first and the second fillings by a chemical etching through the provided access to the second filling.