Patents by Inventor Maud Vinet

Maud Vinet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11941485
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Grant
    Filed: November 24, 2021
    Date of Patent: March 26, 2024
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas Posseme, Louis Hutin, Cyrille Le Royer, François Lefloch, Fabrice Nemouchi, Maud Vinet
  • Patent number: 11823997
    Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.
    Type: Grant
    Filed: September 20, 2021
    Date of Patent: November 21, 2023
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Candice Thomas, Jean Charbonnier, Perceval Coudrain, Maud Vinet
  • Patent number: 11737375
    Abstract: A device including a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.
    Type: Grant
    Filed: April 11, 2022
    Date of Patent: August 22, 2023
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Maud Vinet, Benoît Bertrand, Tristan Meunier
  • Publication number: 20230196167
    Abstract: A spin Qbits quantum device includes a substrate of the semiconductor on insulator type provided with a surface semiconductor layer disposed on an insulating layer, the insulating layer being arranged on an upper face of a semiconductor support layer, and a component formed of one or more quantum islands extending in the surface layer and one or more gate electrodes for electrostatic control of the islands. Front gate electrodes are disposed on the surface layer, and the component includes a back electrostatic control gate formed of a conductive layer lining lateral walls and a bottom of an opening passing through the support layer from a lower face opposite the upper face up to the insulating layer. The conductive layer is disposed at the bottom of the opening in contact with the insulating layer, the conductive layer being disposed in contact with the support layer at the lateral walls.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 22, 2023
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean CHARBONNIER, Myriam ASSOUS, Thomas BEDECARRATS, Nils RAMBAL, Maud VINET
  • Publication number: 20230177376
    Abstract: The present disclosure provides a quantum processing device comprising: one or more functional nanowires, each functional nanowire connected to at least one of a source and a drain; a sensing nanowire spaced from the one or more functional nanowires and connected to at least one of a source and a drain; one or more gate electrodes capacitively coupled with each of the one or more functional nanowires; one or more electrodes capacitively coupled with the sensing nanowire; and a floating coupler positioned between and electrostatically coupling the one or more functional nanowires and the sensing nanowire; and a controller connected to the one or more gates of the sensing nanowire and the one or more gates of the one or more functional nanowires.
    Type: Application
    Filed: March 16, 2021
    Publication date: June 8, 2023
    Applicants: Diraq Pty Ltd, Commissariat a L'energie Atomique Et Aux Energies Alternatives
    Inventors: Maud VINET, Louis HUTIN, William James GILBERT, Andre Luiz SARAIVA DE OLIVEIRA, Christopher Colin ESCOTT
  • Publication number: 20230086994
    Abstract: A semiconductor device includes a layer of a semiconductor material in which is formed an active zone; a plurality of first gates forming a plurality of lines substantially parallel to each other and covering in part the active zone; a plurality of second gates forming a plurality of columns; at least one third gate, designated measurement gate, extending along an axis substantially parallel to the lines of the plurality of lines and in a direction opposite to the lines of the plurality of lines with respect to the active zone, and a first electrode and a second electrode situated on either side of the plurality of measurement gates in the active zone.
    Type: Application
    Filed: August 30, 2022
    Publication date: March 23, 2023
    Inventors: Pierre-André MORTEMOUSQUE, Benoit BERTRAND, Baptiste JADOT, Tristan MEUNIER, Matias URDAMPILLETA, Maud VINET
  • Publication number: 20220359809
    Abstract: A device including: a semiconductor layer comprising first regions delimited by second regions and third regions; first electrostatic control gates including first conductive portions extending parallel to each other, in vertical alignment with the second regions; second electrostatic control gates including second conductive portions extending parallel to each other, in vertical alignment with the third regions; wherein each first gate includes an electrostatic control voltage adjustment element forming two impedances connected in series, one end of one of the impedances being coupled to the first conductive portion of the first gate and one end of the other of the impedances being coupled to a third conductive portion applying an adjustment electric potential to the second impedance, and wherein the value of at least one of the impedances is adjustable.
    Type: Application
    Filed: April 11, 2022
    Publication date: November 10, 2022
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Maud VINET, Benoît BERTRAND, Tristan MEUNIER
  • Publication number: 20220292384
    Abstract: Quantum device, including: a semiconductor portion comprising several first quantum dot regions each disposed between at least two second tunnel barrier regions and placed next to the two second regions; first gates each comprising a first conductive portion; second gates each comprising at least a second conductive portion and a second dielectric disposed between the second conductive portion and the first conductive portion of one of the first gates, such that each of the first gates is disposed between the semi-conductor portion and one of the second gates; wherein the first and second gates are disposed above the first regions or above the second regions, the second gates being solely located in a vertical extension of the first gates.
    Type: Application
    Filed: March 9, 2022
    Publication date: September 15, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Benoit BERTRAND, Biel MARTINEZ I DIAZ, Yann-Michel NIQUET, Maud VINET
  • Publication number: 20220271151
    Abstract: A spin qubit quantum device, comprising: a semiconductor portion comprising a first region disposed between two second regions; a first control gate disposed in direct contact with the first region and configured to control a minimum potential energy level in the first region, and disposed in direct contact with a first face of the semiconductor portion; and second electrostatic control gates, each disposed in direct contact with one of the second regions and configured to control a maximum potential energy level in one of the second regions, and disposed in direct contact with a second face, opposite to the first face, of the semiconductor portion, and wherein the first gate is not aligned with the second gates.
    Type: Application
    Filed: January 18, 2022
    Publication date: August 25, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Thomas BEDECARRATS, Jean CHARBONNIER, Maud VINET, Hélène JACQUINOT, Yann-Michel NIQUET, Candice THOMAS
  • Patent number: 11398593
    Abstract: A process for fabricating an electronic component incorporating double quantum dots and split gates includes providing a substrate surmounted with a stack of a semiconductor layer and of a dielectric layer that is formed above the semiconductor layer. The process also includes forming a mask on the dielectric layer and etching the dielectric layer and the semiconductor layer with the pattern of the mask, so as to form a stack of a semiconductor nanowire and of a dielectric hard mask. Finally, the process includes depositing a gate material on all of the wafer and carrying out a planarization, until the dielectric hard mask is reached, so as to form first and second gates that are electrically insulated from each other on either side of said nanowire.
    Type: Grant
    Filed: October 17, 2018
    Date of Patent: July 26, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Sylvain Barraud, Louis Hutin, Maud Vinet
  • Publication number: 20220172093
    Abstract: A method for producing a quantum device comprising providing a substrate having a front face and carrying at least one transistor pattern on the front face thereof, said transistor pattern comprising, in a stack a gate dielectric on the front face of the substrate, and a gate on the gate dielectric, said gate having a top and sidewalls. The method further includes forming a protective layer at the front face of the substrate, said protective layer being configured to prevent diffusion of at least one metal species in the substrate, forming a metal layer that has, as a main component, at least one metal species, at least on the sidewalls of the gate, said at least one metal species comprising at least one superconducting element, and forming a superconducting region in the gate by lateral diffusion of the at least one superconducting element from the sidewalls of said gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Publication number: 20220173229
    Abstract: A quantum device includes a transistor pattern carried by a substrate, the transistor pattern having, in a stack, a gate dielectric and a superconducting gate on the gate dielectric. The superconducting gate has a base, a tip, sidewalls and at least one superconducting region made of a material that has, as a main component, at least one superconducting element. The superconducting gate also includes a basal portion having a dimension, taken in a first direction of a basal plane that is smaller than a dimension of the tip of the superconducting gate. The transistor pattern further includes at least one dielectric portion made of a dielectric material in contact with the top face of the gate dielectric and the basal portion of the superconducting gate.
    Type: Application
    Filed: November 24, 2021
    Publication date: June 2, 2022
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Nicolas POSSEME, Louis HUTIN, Cyrille LE ROYER, François LEFLOCH, Fabrice NEMOUCHI, Maud VINET
  • Patent number: 11329145
    Abstract: A quantum device with spin qubits, comprising: a semiconductor portion arranged on a buried dielectric layer of a semiconductor-on-insulator substrate also including a semiconductor support layer, wherein first distinct parts each form a confinement region of one of the qubits and are spaced apart from one another by a second part forming a coupling region between the confinement regions of the qubits; front gates each at least partially covering one of the first parts of the semiconductor portion; and wherein the support layer comprises a doped region a part of which is arranged in line with the second part of the semiconductor portion and is self-aligned with respect to the front gates, and forms a back gate controlling the coupling between the confinement regions of the qubits.
    Type: Grant
    Filed: October 15, 2018
    Date of Patent: May 10, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Louis Hutin, Xavier Jehl, Maud Vinet
  • Patent number: 11321626
    Abstract: A method is described for controlling a spin qubit quantum device that includes a semiconducting portion, a dielectric layer covered by the semiconducting portion, a front gate partially covering an upper edge of the semiconducting portion, and a back gate. The method includes, during a manipulation of a spin state, the exposure of the device to a magnetic field B of value such that g·?B·B>min(?(Vbg)). The method also includes the application, on the rear gate, of an electrical potential Vbg of value such that ?(Vbg)<g·?B·B+2|MSO|, and the application, on the front gate, of a confinement potential and an RF electrical signal triggering a change of spin state, with g corresponding to the Landé factor, ?B corresponding to a Bohr magneton, ? corresponding to an intervalley energy difference in the semiconducting portion, and MSO corresponding to the intervalley spin-orbit coupling.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 3, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Leo Bourdet, Louis Hutin, Yann-Michel Niquet, Maud Vinet
  • Publication number: 20220093501
    Abstract: A functional chip includes a substrate including a first face and a second face, the second face of the substrate forming the front face of the functional chip; a first oxide layer on the first face of the substrate; a second oxide layer on the first oxide layer; a first routing level formed on the surface of the second oxide layer in contact with the first oxide layer; a third oxide layer on the second oxide layer wherein a semiconductor component is inserted; a rear face formed by the surface of the third oxide layer opposite the second oxide layer, the rear face including superconductor routing tracks surrounded at least partially by one or more conductor routing tracks, the semiconductor component being connected to the superconductor routing tracks via superconductor vias and the conductor routing tracks of the rear face being connected to the routing level via conductor vias.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 24, 2022
    Inventors: Candice THOMAS, Jean CHARBONNIER, Perceval COUDRAIN, Maud VINET
  • Publication number: 20220093500
    Abstract: An integrated structure intended to connect a plurality of semiconductor devices, the integrated structure including a substrate, a first face and a second face, the first face being intended to receive the semiconductor devices, the integrated structure including, at the first face, at least one routing level, the routing level or levels including: at least one first conductor routing track in a conductor material; and at least one first superconductor routing track made from a superconductor material.
    Type: Application
    Filed: September 20, 2021
    Publication date: March 24, 2022
    Inventors: Candice THOMAS, Jean CHARBONNIER, Perceval COUDRAIN, Maud VINET
  • Patent number: 11264479
    Abstract: A method of production of a field-effect transistor from a stack of layers forming a semiconductor-on-insulator type substrate, the stack including a superficial layer of an initial thickness, made of a crystalline semiconductor material and covered with a protective layer, the method including: defining, by photolithography, a gate pattern in the protective layer; etching the gate pattern into the superficial layer to leave a thickness of the layer of semiconductor material in place, the thickness defining a height of a conduction channel of the field-effect transistor; forming a gate in the gate pattern; forming, in the superficial layer and on either side of the gate, source and drain zones, while preserving, in the zones, the initial thickness of the superficial layer.
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: March 1, 2022
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Laurent Grenouillet, Maud Vinet, Romain Wacquez
  • Patent number: 11088259
    Abstract: A method of fabricating an electronic component with multiple quantum islands is provided, including supplying a substrate on which rests a nanowire made of semiconductor material not intentionally doped, the nanowire having at least two main control gates resting thereon so as to form respective qubits in the nanowire under the two main control gates, the two main control gates being separated by a groove, top and lateral faces of the two main control gates and a bottom of the groove being covered by a dielectric layer; depositing a conductive material in the groove and on the top of the two main control gates; and planarizing down to the dielectric layer on the top of the two main control gates, so as to obtain an element made of conductive material self-aligned between the main control gates.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: August 10, 2021
    Assignee: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Louis Hutin, Sylvain Barraud, Benoit Bertrand, Maud Vinet
  • Patent number: 11011425
    Abstract: A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 18, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Perrine Batude, Francois Andrieu, Maud Vinet
  • Patent number: 10930562
    Abstract: A connection structure for microelectronic device with superposed semi-conductor layers including a conductor via that connects a lower face of an upper semi-conductor layer and an underlying conducting zone, the connection structure further including a silicide zone in contact with a lower face or with an inner face of the layer of the upper semi-conductor layer.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: February 23, 2021
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Claire Fenouillet-Beranger, Fabrice Nemouchi, Maud Vinet