Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).

Abstract: An electronic device may include a substrate, a buried oxide (BOX) layer overlying the substrate, at least one semiconductor device overlying the BOX layer, and at least one shallow trench isolation (STI) region in the substrate and adjacent the at least one semiconductor device. The at least one STI region defines a sidewall surface with the substrate and may include an oxide layer lining a bottom portion of the sidewall surface, a nitride layer lining a top portion of the sidewall surface above the bottom portion, and an insulating material within the nitride and oxide layers.

Abstract: A method for making a three-dimensional integrated electronic circuit is provided, including making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that it is disposed between the first and second dielectric layers, and a second semiconductor layer disposed on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the first electronic component to the first elect

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

Abstract: A fin MOS transistor is made from an SOI-type structure that includes a semiconductor layer on a silicon oxide layer coating a semiconductor support. A trench formed from the surface of the semiconductor layer delimits at least one fin in the semiconductor layer, that trench extending at least to an upper surface of the semiconductor support. Etched recesses in sides of a portion of the silicon oxide layer located under the fin are filled with a material selectively etchable over silicon oxide.

Abstract: A method for manufacturing a microelectronic device with transistors of different types having raised source and drain regions and different overlap regions.

Abstract: An integrated circuit, including: a UTBOX layer; a first cell, including: FDSOI transistors; a first STI separating the transistors; a first ground plane located beneath one of the transistors and beneath the UTBOX layer; a first well; a second cell, including: FDSOI transistors; a second STI separating the transistors; a second ground plane located beneath one of the transistors and beneath the UTBOX layer; a second well; a third STI separating the cells, reaching the bottom of the first and second wells; a deep well extending continuously beneath the first and second wells, having a portion beneath the third STI whose doping density is at least 50% higher than the doping density of the deep well beneath the first and second STIs.

Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.

Abstract: The invention provides a method of etching a crystalline semiconductor material (114), the method being characterized in that it comprises: at least one ion implantation performed by implanting a plurality of ions (121) in at least one volume (113) of the semiconductor material (114) in such a manner as to make the semiconductor material amorphous in the at least one implanted volume (113), and as to keep the semiconductor material (114) in a crystalline state outside (112) the at least one implanted volume (113); and at least one chemical etching for selectively etching the amorphous semiconductor material relative to the crystalline semiconductor material, so as to remove the semiconductor material in the at least one volume (113) and so as to keep the semiconductor material outside (112) the at least one volume (113).

Abstract: A shallow trench is formed to extend into a handle substrate of a semiconductor-on-insulator (SOI) layer. A dielectric liner stack of a dielectric metal oxide layer and a silicon nitride layer is formed in the shallow trench, followed by deposition of a shallow trench isolation fill portion. The dielectric liner stack is removed from above a top surface of a top semiconductor portion, followed by removal of a silicon nitride pad layer and an upper vertical portion of the dielectric metal oxide layer. A divot laterally surrounding a stack of a top semiconductor portion and a buried insulator portion is filled with a silicon nitride portion. Gate structures and source/drain structures are subsequently formed. The silicon nitride portion or the dielectric metal oxide layer functions as a stopping layer during formation of source/drain contact via holes, thereby preventing electrical shorts between source/drain contact via structures and the handle substrate.

Abstract: The invention relates to a process for fabricating an integrated circuit (1), comprising the steps of: providing a substrate (100), the substrate being equipped with first and second dummy gates and with an encapsulation layer (106); removing the first and second dummy gates in order to make first and second grooves (23, 33) in said encapsulation layer (106); simultaneously depositing a gate insulating layer (107) at least in the bottom of the first groove and on a side wall of the second groove; forming a gate electrode of said transistor (2) in the first groove, forming source and drain electrodes of said transistor on either side of said gate electrode, forming first and second electrodes of said memory cell on either side of said gate insulating layer deposited on a side wall of the second groove.

Abstract: Methods and structures for forming uniaxially-strained, nanoscale, semiconductor bars from a biaxially-strained semiconductor layer are described. A spatially-doubled mandrel process may be used to form a mask for patterning dense, narrow trenches through the biaxially-strained semiconductor layer. The resulting slicing of the biaxially-strained layer enhances carrier mobility and can increase device performance.

Abstract: A method for making a transistor in which: a) on a substrate, at least one semi-conductor structure is made, which is formed by a stack comprising alternating layer(s) based on at least one first semi-conductor material and layer(s) based on at least one second semi-conductor material different from the first semi-conductor material, b) a zone of the structure is made amorphous using implantations, the zone made amorphous comprising one or more portions of one or more layers based on the second semi-conductor material, c) the portions are removed by selectively etching a second semi-conductor material made amorphous towards the first semi-conductor material (FIG. 2L).

Abstract: Single-electron transistor comprising at least: first semiconductor portions forming source and drain regions, a second semiconductor portion forming at least one quantum island, third semiconductor portions forming tunnel junctions between the second semiconductor portion and the first semiconductor portions, a gate and a gate dielectric located on at least the second semiconductor portion, in which a thickness of each of the first semiconductor portions is greater than the thickness of the second semiconductor portion, and in which a thickness of the second semiconductor portion is greater than the thickness of each of the third semiconductor portions.

Abstract: The present invention relates to a pair of transistors wherein each transistor of said transistor pair is made of several sub-transistors, and each sub-transistor of a transistor has a sub-transistor channel length and has a sub-transistor channel width, said sub-transistor channel length being substantially equal to the transistor channel length, and said sub-transistor channel width being smaller than the transistor channel width, so that the sum of the sub-transistor channel widths of the sub-transistors of a transistor is substantially equal to the channel width of said transistor, wherein each sub-transistor (43) of a transistor of said transistor pair is spaced apart from at least one adjoining sub-transistor (44) of the other transistor of said transistor pair by a distance D less than half the transistor channel width, said distance d between two sub-transistors (43, 44) being measured between the respective center of the channels of said sub-transistors.

Abstract: A method of producing a microelectronic device in a substrate including a first semiconductor layer, a first dielectric layer, and a second semiconductor layer, including: etching a trench through the first semiconductor layer, the first dielectric layer, and a part of the second semiconductor layer, defining one active region, and such that, at the level of the second semiconductor layer, a part of the trench extends under a part of the active region; deposition of one second dielectric layer in the trench; etching the second dielectric layer such that remaining portions of the second dielectric layer forms portions of dielectric material extending under a part of the active region; deposition of a third dielectric layer in the trench such that the trench is filled with the dielectric materials of the second and third dielectric layers and forms an isolation trench.

Abstract: A method of producing a microelectronic device in a substrate comprising a first semiconductor layer, a dielectric layer and a second semiconductor layer, comprising the following steps: etching a trench through the first semiconductor layer, the dielectric layer and a part of the thickness of the second semiconductor layer, thus defining, in the first semiconductor layer, one active region of the microelectronic device, ionic implantation in one or more side walls of the trench, at the level of the second semiconductor layer, modifying the crystallographic properties and/or the chemical properties of the implanted semiconductor, etching of the implanted semiconductor such that at least a part of the trench extends under a part of the active region, —filling of the trench with a dielectric material, forming an isolation trench surrounding the active region and comprising portions extending under a part of the active region.

Abstract: The substrate is provided with a first semiconducting area partially covered by a first masking pattern to define a protected surface and an open surface. A continuous layer of silicon-germanium is deposited in non-selective manner on the first semiconducting area and on the first gate pattern. The continuous silicon-germanium layer forms an interface with the first semiconducting area. A diffusion/condensation annealing is performed to make the germanium atoms diffuse from the silicon-germanium layer to the open surface of the first semiconducting area. The masking pattern is a gate stack of the transistor or is used to define the shape of the gate stack in an electrically insulating layer so as to form a self-aligned gate stack with the source and drain areas.

Abstract: A method for making a three-dimensional integrated electronic circuit comprising steps for: making a first electrically conductive portion on a first dielectric layer covering a first semiconductor layer; then making a second dielectric layer covering the first electrically conductive portion such that the first electrically conductive portion is arranged between the first and second dielectric layers, and a second semiconductor layer arranged on the second dielectric layer; then making a first electronic component in the second semiconductor layer, and a second electronic component in the first semiconductor layer; then making an electrical interconnection electrically linking the first and second electronic components together, of which a first part passes through the first dielectric layer and electrically connects the second electronic component to the first electrically conductive portion and of which a second part passes through a part of the second dielectric layer and electrically connects the firs

Abstract: A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material.