Abstract: This invention relates to an improved microelectronic method for making a double gate structure for a transistor, and particularly gate patterns (108a,128a,208a,228a,308a,328a) with a critical dimension less than the critical dimension of the transistor channel zone (104b). This method particularly includes a step to reduce double gate patterns, using isotropic etching. The invention also relates to a microelectronic device obtained using such a method.

Abstract: A process for fabricating a transistor that includes a gate located in the immediate proximity of a dielectric includes a step of etching a layer of gate material. The gate etching step includes plasma etching of the gate layer over the major portion of its thickness so as to laterally define the gate and chemical etching of a residual portion of the gate layer so as to define the gate as far as the dielectric.

Abstract: A transistor device with a mobile suspended gate, the device comprising means for piezoelectric actuation of the gate, and a method for producing such a device.

Abstract: The present application relates to a non-volatile random-access memory cell equipped with a suspended mobile gate and with piezoelectric means for operating the gate.

Abstract: A method for insulating patterns formed in a thin film made of a first oxidizable semi-conducting material, with a thickness less than or equal to 20 nm and preferably less than or equal to 10 nm, successively comprises: formation, on the thin film, of a mask defining, in the thin film, free zones and zones covered by the mask designed to substantially form the patterns, selective formation, at the level of the free zones of the thin film, of an additional layer formed by an oxide of a second semi-conducting material, oxidization of the free zones of the thin film, removal of the mask so as to release the thin film patterned in the form of patterns insulated by oxidized zones. The first and second semi-conducting materials can be identical and the step of selective formation of the additional layer can be performed by selective epitaxial growth of the free zones of the thin film.

Abstract: A device for measuring the resistivity ?c of an interface between a semiconductor and a metal, comprising at least: one dielectric layer, at least one semiconductor-based element of a substantially rectangular shape, which is arranged on the dielectric layer, having a lengthwise L and widthwise W face in contact with the dielectric layer and having a thickness t, at least two interface portions containing the metal or an alloy of said semiconductor and said metal, each of the two opposing faces of the semiconductor element, having a surface equal to t×W and being perpendicular to the face in contact with the dielectric layer, being completely covered by one of the interface portions.

Abstract: An improved microelectronic device, and method for making such a microelectronic device. The device includes one or plural transistors and piezoelectric mechanisms, with an arrangement capable of applying a variable mechanical strain on transistor channels.

Abstract: Semiconductor device comprising at least: one substrate, a transistor comprising at least one source region, one drain region, one channel and one gate, a planar layer based on at least one piezoelectric material, resting at least on the gate and capable of inducing at least mechanical strain on the transistor channel, in a direction that is substantially perpendicular to the plane of a face of the piezoelectric layer situated on the gate side, piezoelectric layer being arranged between two biasing electrodes, one of the two biasing electrodes being formed by a first layer based on at least one electrically conductive material such that the piezoelectric layer is arranged between this first conductive layer and the gate of the transistor.

Abstract: A method for forming patterns which are aligned on either side of a thin film deposited on a substrate. The method includes depositing a first pattern layer on the thin film which may occur before or after the local etching of the thin film to form a first marking. The method includes etching the first pattern layer in order to form a first pattern and depositing a first bonding layer for covering the first marking and the first pattern. The method may include suppressing the substrate as well as etching the first bonding layer to form a second marking at the location of the first marking. The method includes depositing a second pattern layer, and etching the second pattern layer to form the second pattern.

Abstract: Method of producing a transistor, comprising in particular the steps of: producing a first etching mask on a gate layer, one edge of the first mask forming a pattern of the first edge of a gate of the transistor, etching the gate layer according to the first etching mask, first ion implantation in a part of the substrate not covered by the gate layer, trimming the first etching mask over a length equal to a gate length of the transistor, producing a second etching mask on the gate layer, removing the first etching mask etching the gate layer according to the second etching mask, second ion implantation in another part of the substrate.

Abstract: The invention concerns a random access memory cell comprising: at least one first plurality of symmetrical dual-gate transistors (TL1T, TL1F, TD1T, TD1F, TL2T, TL2F) forming a flip-flop, at least a first asymmetric dual-gate access transistor (TA1T, TAW1T) and at least a second asymmetric dual-gate access transistor (TA1F, TAW1F) disposed respectively between a first bit line (BLT, WBLT) and a first storage node (T), and between a second bit line (BLF, WBLF) and a second storage node (F), a first gate of the first access transistor (TA1T, TAW1T) and a first gate of the second access transistor (TA1F, TAW1F) being connected to a first word line (WL, WWL) able to route a biasing signal, a second gate (TA1F, TAW1F) of the first access transistor connected to the second storage node (F) and a second gate of the second access transistor connected to the first storage node (T).

Abstract: The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.

Abstract: A process for fabricating a transistor comprising a gate (50?) located in the immediate proximity of a dielectric (46) includes a step of etching a layer of gate material. This gate etching step comprises the following steps: plasma etching of this layer over the major portion of its thickness so as to laterally define the gate (50?); chemical etching of a residual portion (48?) of this layer so as to define this gate as far as the dielectric (46).

Abstract: The method successively comprises production, on a substrate, of a stack of layers comprising at least one first layer made from germanium and silicon compound initially having a germanium concentration comprised between 10% and 50%. The first layer is arranged between second layers having germanium concentrations comprised between 0% and 10%. Then a first zone corresponding to the germanium-based element and having at least a first lateral dimension comprised between 10 nm and 500 nm is delineated by etching in said stack. Then at least lateral thermal oxidization of the first zone is performed so that a silica layer forms on the surface of the first zone and that, in the first layer, a central zone of condensed germanium forms, constituting the germanium-based element.

Abstract: The invention relates to a method for forming patterns (11, 22) aligned on either side of a thin film (3) deposited on a substrate (1), said method comprising: depositing a first pattern layer (5) on the thin film (3), the deposition of the first pattern layer preceding or following local etching of the thin film (3) in order to form a first marking, etching the first pattern layer in order to form a first pattern (11), depositing a first bonding layer (3) for covering the first marking (8) and the first pattern (11), suppressing the substrate (1), etching the first bonding layer (13) in order to form a second marking (16) at the location of the first marking (8), depositing a second pattern layer (18), and etching the second pattern layer (18) in order to form the second pattern (22).

Abstract: A method for insulating patterns formed in a thin film made of a first oxidizable semi-conducting material, with a thickness less than or equal to 20 nm and preferably less than or equal to 10 nm, successively comprises: formation, on the thin film, of a mask defining, in the thin film, free zones and zones covered by the mask designed to substantially form the patterns, selective formation, at the level of the free zones of the thin film, of an additional layer formed by an oxide of a second semi-conducting material, oxidization of the free zones of the thin film, removal of the mask so as to release the thin film patterned in the form of patterns insulated by oxidized zones. The first and second semi-conducting materials can be identical and the step of selective formation of the additional layer can be performed by selective epitaxial growth of the free zones of the thin film.

Abstract: A method is provided for fabricating a thin layer element, in which a layer of a first material supports a pattern of a second material having a thickness of less than 15 nm, including a step of doping by implanting a chemical species over at least a portion of the layer-pattern assembly to stabilize the pattern on the layer.

Abstract: Method for forming a structure provided with at least one zone of one or several semiconductor nanocrystals (13). It consists in: exposing with a beam of electrons (11) at least one zone (12) of a semiconductor film (1) lying on an electrically insulating support (2), the exposed zone (12) contributing to defining at least one dewetting zone (10) of the film (1), annealing the film (1) at high temperature in such a way that the dewetting zone (10) retracts giving the zone of one or several nanocrystals (13).

Abstract: The invention relates to a thin film having a thickness of less than 10 nm, made of oxidizable semi-conductor material and patterned in the form of patterns. To prevent the dewetting phenomenon of said patterns, lateral oxidized zones are arranged at the periphery of each pattern of the thin film so as to form an anchoring. This anchoring can be achieved by forming an oxide layer over the whole of the thin film and then depositing a nitride layer. Then the nitride and oxide layers and the thin film are patterned and the thin film is laterally oxidized so that each pattern of the thin film comprises, at the periphery thereof, an oxidized zone of predetermined width. The nitride and oxide layers are then removed so as to release the patterns oxidized at their periphery.