Patents by Inventor Mauro Kobrinsky

Mauro Kobrinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250218937
    Abstract: Transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. Transistor structures may have a gate electrode thickness under a channel region one-and-a-half or two times greater than a thickness between adjacent nanoribbons in the channel region. Front- and back-side spacer layers with a same composition may have a discernible interface. Contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to gate electrodes revealed on a substrate back side.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Shaun Mills, Joseph D’Silva, Mauro Kobrinsky, Umang Desai
  • Publication number: 20250221020
    Abstract: An integrated circuit (IC) device includes transistors between front- and back-side interconnect layers and having source and/or drain regions with front- and back-side contacts. The transistors may be between isolation structures on a same pitch as the transistor gates, sources, and drains. Via structures adjacent to the transistors couple between the front- and back-side interconnect layers. The transistors and isolation and via structures may be utilized in various logic cells. Transistors having front- and back-side source and/or drain contacts may include vias through or alongside the source and/or drain regions.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Sanjay Natarajan, Mauro Kobrinsky, Cory Weber, Vishal Tiwari, Shaun Mills, Joseph D’Silva, Ehren Mannebach
  • Publication number: 20250218869
    Abstract: Transistor structures between and coupled to front- and back-side interconnect layers may have precisely aligned arrays of contacts and dielectric structures over and under the transistor structures. Back-side dielectric plugs may electrically isolate source and drain regions contacted on the front side from back-side interconnect lines. Back-side dielectric plugs may have a seam indicating plug formation from the back side, and the seam may be on a side contacting a back-side interconnect line. Spacer layers may insulate back-side gate contacts from adjacent back-side contacts. Contacts and dielectric structures on a back side may be formed using directed self-assembly of sacrificial materials aligned to sacrificial structures on source and drain regions and revealed on a substrate back side.
    Type: Application
    Filed: December 29, 2023
    Publication date: July 3, 2025
    Applicant: Intel Corporation
    Inventors: Ehren Mannebach, Shaun Mills, Joseph D’Silva, Mauro Kobrinsky
  • Patent number: 12342574
    Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: June 24, 2025
    Assignee: Intel Corporation
    Inventors: Koustav Ganguly, Ryan Keech, Subrina Rafique, Glenn A. Glass, Anand S. Murthy, Ehren Mannebach, Mauro Kobrinsky, Gilbert Dewey
  • Patent number: 12334392
    Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.
    Type: Grant
    Filed: August 7, 2019
    Date of Patent: June 17, 2025
    Inventors: Kevin Lai Lin, Mauro Kobrinsky, Mark Anders, Himanshu Kaul, Ram Krishnamurthy
  • Patent number: 12315794
    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
    Type: Grant
    Filed: December 23, 2022
    Date of Patent: May 27, 2025
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Mauro Kobrinsky, Shawna Liff, Johanna Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj
  • Patent number: 12288746
    Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: April 29, 2025
    Assignee: Intel Corporation
    Inventors: Adel Elsherbini, Mauro Kobrinsky, Shawna Liff, Johanna Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj
  • Publication number: 20250113580
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to contacting source and drain transistor structures from the device backside at small dimensions and cell sizes. A first subset of dummy contact structures are removed and backfilled with contact metal and a first etch stop material. A second subset of dummy contact structures are removed and backfilled with contact metal and a second etch stop material. Subsequent metallization contacts to the first and second contacts are made using two masking/selective etch processes such that any misalignment to the other contact type does not allow contact due to the pertinent etch stop material.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Applicant: Intel Corporation
    Inventors: Leonard Guler, Shaun Mills, Joseph D'Silva, Ehren Mannebach, Mauro Kobrinsky, Charles H. Wallace, Kalpesh Mahajan, Vivek Vishwakarma, Dincer Unluer, Jessica Panella
  • Patent number: 12211794
    Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.
    Type: Grant
    Filed: January 25, 2022
    Date of Patent: January 28, 2025
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Anil Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
  • Patent number: 12199143
    Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.
    Type: Grant
    Filed: December 26, 2019
    Date of Patent: January 14, 2025
    Assignee: Intel Corporation
    Inventors: Biswajeet Guha, Mauro Kobrinsky, Patrick Morrow, Oleg Golonzka, Tahir Ghani
  • Publication number: 20240332379
    Abstract: Devices, transistor structures, systems, and techniques are described herein related to backside contacts for field effect transistors formed using a backside contact etch prior to cavity spacer formation. A transistor includes semiconductor structures such as nanoribbons extending between a source and a drain. A spacer material is between a gate and the source/drain as cavity spacer fill. The spacer material is also between a portion of a backside contact and a portion of the source/drain, to eliminate a short between the backside contact and the gate.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Applicant: Intel Corporation
    Inventors: Shaun Mills, Ehren Mannebach, Mauro Kobrinsky, Kai Loon Cheong, Makram Abd El Qader
  • Patent number: 12107170
    Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.
    Type: Grant
    Filed: November 2, 2021
    Date of Patent: October 1, 2024
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
  • Publication number: 20240243052
    Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.
    Type: Application
    Filed: March 29, 2024
    Publication date: July 18, 2024
    Applicant: Intel Corporation
    Inventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
  • Patent number: 11985909
    Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.
    Type: Grant
    Filed: June 10, 2019
    Date of Patent: May 14, 2024
    Assignee: Intel Corporation
    Inventors: Elijah Karpov, Mauro Kobrinsky
  • Patent number: 11948874
    Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.
    Type: Grant
    Filed: June 26, 2020
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
  • Publication number: 20240006302
    Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.
    Type: Application
    Filed: July 1, 2022
    Publication date: January 4, 2024
    Applicant: Intel Corporation
    Inventors: Richard H. Livengood, Muhammad Usman Raza, Waqas Ali, Tahir Malik, Shida Tan, Martin Von Haartman, Mauro Kobrinsky, Amir Raveh, Clifford J. Engle
  • Patent number: 11830788
    Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: November 28, 2023
    Assignee: Intel Corporation
    Inventors: Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher Jezewski, Mauro Kobrinsky, Kevin Lin, Abhishek Anil Sharma
  • Patent number: 11721554
    Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 18, 2019
    Date of Patent: August 8, 2023
    Assignee: Intel Corporation
    Inventors: Anant Jahagirdar, Chytra Pawashe, Aaron Lilak, Myra McDonnell, Brennen Mueller, Mauro Kobrinsky
  • Publication number: 20230197601
    Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Applicant: Intel Corporation
    Inventors: Jiun-Ruey Chen, Christopher Jezewski, John Plombon, Miriam Reshotko, Mauro Kobrinsky, Scott B. Clendenning
  • Publication number: 20220415818
    Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Applicant: Intel Corporation
    Inventors: Carl Naylor, Jasmeet Chawla, Matthew Metz, Sean King, Ramanan Chebiam, Mauro Kobrinsky, Scott Clendenning, Sudarat Lee, Christopher Jezewski, Sunny Chugh, Jeffery Bielefeld