Patents by Inventor Mauro Kobrinsky
Mauro Kobrinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11948874Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.Type: GrantFiled: June 26, 2020Date of Patent: April 2, 2024Assignee: Intel CorporationInventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
-
Publication number: 20240006302Abstract: Techniques and structures are disclosed related to coupling to gate-all-around transistors for test and/or debug of an integrated circuit. The gate-all-around transistors, which may also be referred to as 3D stacked transistors or ribbon-FET transistors are contacted directly from the back side or they are contacted using a dedicated probe point on the back side of the gate-all-around transistors. Such contact may be made to probe the devices and/or to provide edit wires to modify the integrated circuit.Type: ApplicationFiled: July 1, 2022Publication date: January 4, 2024Applicant: Intel CorporationInventors: Richard H. Livengood, Muhammad Usman Raza, Waqas Ali, Tahir Malik, Shida Tan, Martin Von Haartman, Mauro Kobrinsky, Amir Raveh, Clifford J. Engle
-
Patent number: 11830788Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: GrantFiled: May 25, 2021Date of Patent: November 28, 2023Assignee: Intel CorporationInventors: Carl Naylor, Ashish Agrawal, Urusa Alaan, Christopher Jezewski, Mauro Kobrinsky, Kevin Lin, Abhishek Anil Sharma
-
Patent number: 11721554Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.Type: GrantFiled: March 18, 2019Date of Patent: August 8, 2023Assignee: Intel CorporationInventors: Anant Jahagirdar, Chytra Pawashe, Aaron Lilak, Myra McDonnell, Brennen Mueller, Mauro Kobrinsky
-
Publication number: 20230197601Abstract: Metallization interconnect structures, integrated circuit devices, and methods related to high aspect ratio interconnects are discussed. A self assembled monolayer is selectively formed on interlayer dielectric sidewalls of an opening that exposes an underlying metallization structure. A first metal is formed on the underlying metallization structure and within only a bottom portion of the self assembled monolayer. The exposed portion of the self assembled monolayer is removed and a second metal is formed over the first metal.Type: ApplicationFiled: December 21, 2021Publication date: June 22, 2023Applicant: Intel CorporationInventors: Jiun-Ruey Chen, Christopher Jezewski, John Plombon, Miriam Reshotko, Mauro Kobrinsky, Scott B. Clendenning
-
Publication number: 20230130935Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.Type: ApplicationFiled: December 23, 2022Publication date: April 27, 2023Applicant: Intel CorporationInventors: Adel ELSHERBINI, Mauro KOBRINSKY, Shawna LIFF, Johanna SWAN, Gerald PASDAST, Sathya Narasimman TIAGARAJ
-
Publication number: 20220415795Abstract: Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Mohit Haran, Charles Wallace, Leanord Guler, Sukru Yemenicioglu, Mauro Kobrinsky, Tahir Ghani
-
Publication number: 20220415880Abstract: Substrate-less diode, bipolar and feedthrough integrated circuit structures, and methods of fabricating substrate-less diode, bipolar and feedthrough integrated circuit structures, are described. For example, a substrate-less integrated circuit structure includes a semiconductor structure. A plurality of gate structures is over the semiconductor structure. A plurality of P-type epitaxial structures is over the semiconductor structure. A plurality of N-type epitaxial structures is over the semiconductor structure. One or more open locations is between corresponding ones of the plurality of gate structures. A backside contact is connected directly to one of the pluralities of P-type and N-type epitaxial structures.Type: ApplicationFiled: June 24, 2021Publication date: December 29, 2022Inventors: Ayan KAR, Kalyan KOLLURU, Nicholas THOMSON, Rui MA, Benjamin ORR, Nathan JACK, Mauro KOBRINSKY, Patrick MORROW, Chung-Hsun LIN
-
Publication number: 20220416050Abstract: Embodiments disclosed herein include semiconductor devices with improved contact resistances. In an embodiment, a semiconductor device comprises a semiconductor channel, a gate stack over the semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, and contacts over the source region and the drain region. In an embodiment, the contacts comprise a silicon germanium layer, an interface layer over the silicon germanium layer, and a titanium layer over the interface layer.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Inventors: Debaleena NANDI, Cory BOMBERGER, Gilbert DEWEY, Anand S. MURTHY, Mauro KOBRINSKY, Rushabh SHAH, Chi-Hing CHOI, Harold W. KENNEL, Omair SAADAT, Adedapo A. ONI, Nazila HARATIPOUR, Tahir GHANI
-
Publication number: 20220415818Abstract: Integrated circuitry interconnect structures comprising a first metal and a graphene cap over a top surface of the first metal. Within the interconnect structure an amount of a second metal, nitrogen, or silicon is greater proximal to an interface of the graphene cap. The presence of the second metal, nitrogen, or silicon may improve adhesion of the graphene to the first metal and/or otherwise improve electromigration resistance of a graphene capped interconnect structure. The second metal, nitrogen, or silicon may be introduced into the first metal during deposition of the first metal, or during a post-deposition treatment of the first metal. The second metal, nitrogen, or silicon may be introduced prior to, or after, capping the first metal with graphene.Type: ApplicationFiled: June 25, 2021Publication date: December 29, 2022Applicant: Intel CorporationInventors: Carl Naylor, Jasmeet Chawla, Matthew Metz, Sean King, Ramanan Chebiam, Mauro Kobrinsky, Scott Clendenning, Sudarat Lee, Christopher Jezewski, Sunny Chugh, Jeffery Bielefeld
-
Patent number: 11532558Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.Type: GrantFiled: September 27, 2019Date of Patent: December 20, 2022Assignee: Intel CorporationInventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
-
Patent number: 11410928Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.Type: GrantFiled: June 7, 2018Date of Patent: August 9, 2022Assignee: Intel CorporationInventors: Mark Bohr, Mauro Kobrinsky, Marni Nabors
-
Publication number: 20220199516Abstract: Embodiments of the disclosure are in the field of integrated circuit structure fabrication. In an example, an integrated circuit structure includes a plurality of conductive interconnect lines above a substrate, individual ones of the conductive interconnect lines having a top and sidewalls. An etch stop layer is on the top and along an entirety of the sidewalls of the individual ones of the conductive interconnect lines.Type: ApplicationFiled: December 21, 2020Publication date: June 23, 2022Inventors: Ramanan V. CHEBIAM, Colin T. CARVER, Kevin Lai LIN, Mauro KOBRINSKY
-
Publication number: 20220148917Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek Anil SHARMA, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
-
Publication number: 20220102268Abstract: Integrated circuit interconnect structures including a metallization line with a bottom barrier material, and a metallization via lacking a bottom barrier material. Barrier material at a bottom of the metallization line may, along with barrier material on a sidewall of the metallization line, mitigate the diffusion or migration of fill metal from the line. An absence of barrier material at a bottom of the via may reduce via resistance and/or facilitate the use of a highly resistive barrier material that may enhance the scalability of interconnect structures. A number of masking materials and patterning techniques may be integrated into a dual damascene interconnect process to provide for both a barrier material and a low resistance via unburden by the barrier material.Type: ApplicationFiled: September 25, 2020Publication date: March 31, 2022Applicant: Intel CorporationInventors: Urusa Alaan, Kevin L. Lin, Miriam Reshotko, Sarah Atanasov, Christopher Jezewski, Carl Naylor, Mauro Kobrinsky, Hui Jae Yoo
-
Patent number: 11276644Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.Type: GrantFiled: December 17, 2018Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
-
Publication number: 20220059702Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: ApplicationFiled: November 2, 2021Publication date: February 24, 2022Applicant: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
-
Publication number: 20210408246Abstract: Embodiments disclosed herein include transistor devices and methods of making such devices. In an embodiment, the transistor device comprises a stack of semiconductor channels with a first source/drain region on a first end of the semiconductor channels and a second source/drain region on a second end of the semiconductor channels. In an embodiment, the first source/drain region and the second source/drain region have a top surface and a bottom surface. In an embodiment, the transistor device further comprises a first source/drain contact electrically coupled to the top surface of the first source/drain region, and a second source/drain contact electrically coupled to the bottom surface of the second source/drain region. In an embodiment, the second source/drain contact is separated from the second source/drain region by an interfacial layer.Type: ApplicationFiled: June 25, 2020Publication date: December 30, 2021Inventors: Koustav GANGULY, Ryan KEECH, Subrina RAFIQUE, Glenn A. GLASS, Anand S. MURTHY, Ehren MANNEBACH, Mauro KOBRINSKY, Gilbert DEWEY
-
Publication number: 20210407895Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Applicant: Intel CorporationInventors: Kevin L. Lin, Sukru Yemenicioglu, Patrick Morrow, Richard Schenker, Mauro Kobrinsky
-
Publication number: 20210398977Abstract: Integrated circuitry comprising interconnect metallization on both front and back sides of a gate-all-around (GAA) transistor structure lacking at least one active bottom channel region. Bottom channel regions may be depopulated from a GAA transistor structure following removal of a back side substrate that exposes an inactive portion of a semiconductor fin. During back-side processing, one or more bottom channel region may be removed or rendered inactive through dopant implantation. Back-side processing may then proceed with the interconnection of one or more terminal of the GAA transistor structures through one or more levels of back-side interconnect metallization.Type: ApplicationFiled: June 18, 2020Publication date: December 23, 2021Applicant: Intel CorporationInventors: Varun Mishra, Peng Zheng, Aaron Lilak, Tahir Ghani, Harold Kennel, Mauro Kobrinsky