Patents by Inventor Mauro Kobrinsky
Mauro Kobrinsky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11189585Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.Type: GrantFiled: December 4, 2019Date of Patent: November 30, 2021Assignee: Intel CorporationInventors: Brennen K. Mueller, Adel Elsherbini, Mauro Kobrinsky, Johanna Swan, Shawna Liff, Pooya Tadayon
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Publication number: 20210351105Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: ApplicationFiled: May 25, 2021Publication date: November 11, 2021Inventors: Carl Naylor, Ashish AGRAWAL, Urusa ALAAN, Christopher JEZEWSKI, Mauro KOBRINSKY, Kevin LIN, Abhishek Anil SHARMA
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Patent number: 11171239Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: GrantFiled: September 13, 2019Date of Patent: November 9, 2021Assignee: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
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Patent number: 11164809Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: GrantFiled: December 17, 2018Date of Patent: November 2, 2021Assignee: Intel CorporationInventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
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Publication number: 20210202377Abstract: An integrated circuit device may be formed including an electronic substrate and a metallization structure on the electronic substrate, wherein the metallization structure includes a first level comprising a first dielectric material layer, a second level on the first level, wherein the second level comprises a second dielectric material layer, a third level on the second level, wherein the third level comprises a third dielectric material layer, at least one power/ground structure in the second level, and at least one skip level via extending at least partially through the first dielectric material layer of the first level, through the second dielectric layer of the second level, and at least partially through the third dielectric material layer of the third level, wherein the at least one skip level via comprises a continuous conductive material.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Applicant: Intel CorporationInventors: Adel Elsherbini, Mauro Kobrinsky, Shawna Liff, Johanna Swan, Gerald Pasdast, Sathya Narasimman Tiagaraj
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Publication number: 20210202696Abstract: Gate-all-around integrated circuit structures having a removed substrate, and methods of fabricating gate-all-around integrated circuit structures having a removed substrate, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires. A gate stack surrounds a channel region of the vertical arrangement of horizontal nanowires. A pair of non-discrete epitaxial source or drain structures is at first and second ends of the vertical arrangement of horizontal nanowires. A pair of dielectric spacers is between the pair of non-discrete epitaxial source or drain structures and the gate stack. The pair of dielectric spacers and the gate stack have co-planar top surfaces. The pair of dielectric spacers, the gate stack and the pair of non-discrete epitaxial source or drain structures have co-planar bottom surfaces.Type: ApplicationFiled: December 26, 2019Publication date: July 1, 2021Inventors: Biswajeet GUHA, Mauro KOBRINSKY, Patrick MORROW, Oleg GOLONZKA, Tahir GHANI
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Publication number: 20210175192Abstract: An Integrated Circuit (IC) device comprising a first component, the first component comprising a first dielectric and a plurality of adjacent first interconnect structures within the first dielectric. The IC device comprising a second component, the second component comprising a second dielectric and a plurality of adjacent second interconnect structures within the second dielectric. A first of the second interconnect structures is in direct contact with a first of the first interconnect structures at a bond interface between the first and second components. A second of the first interconnect structures is set back a distance from a plane of the bond interface.Type: ApplicationFiled: December 4, 2019Publication date: June 10, 2021Applicant: Intel CorporationInventors: Brennen K. Mueller, Adel Elsherbini, Mauro Kobrinsky, Johanna Swan, Shawna Liff, Pooya Tadayon
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Patent number: 11018075Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: GrantFiled: December 17, 2018Date of Patent: May 25, 2021Assignee: Intel CorporationInventors: Carl Naylor, Ashish Agrawal, Kevin Lin, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan
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Publication number: 20210098387Abstract: Composite integrated circuit (IC) device structures that include two components coupled through a hybrid bonded composite interconnect structure. The two components may be two different monolithic IC structures (e.g., chips) that are bonded over substantially planar dielectric and metallization interfaces. Composite interconnect metallization features formed at a bond interface may be doped with a metal or chalcogenide dopant. The dopant may migrate to a periphery of the composite interconnect structure and form a barrier material that will then limit outdiffusion of a metal, such as copper, into adjacent dielectric material.Type: ApplicationFiled: September 27, 2019Publication date: April 1, 2021Applicant: Intel CorporationInventors: Carl Naylor, Mauro Kobrinsky, Richard Vreeland, Ramanan Chebiam, William Brezinski, Brennen Mueller, Jeffery Bielefeld
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Publication number: 20210083122Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g., <450° C.). The 2D material may be a chalcogenide of a metal present in the channel material (e.g., ZnSx or ZnSex) or of a metal absent from the channel material when formed from a sacrificial precursor.Type: ApplicationFiled: September 13, 2019Publication date: March 18, 2021Applicant: Intel CorporationInventors: Carl Naylor, Abhishek Sharma, Mauro Kobrinsky, Christopher Jezewski, Urusa Alaan, Justin Weber
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Publication number: 20210043567Abstract: Embodiments disclosed herein include a semiconductor device with interconnects with non-uniform heights. In an embodiment, the semiconductor device comprises a semiconductor substrate, and a back end of line (BEOL) stack over the semiconductor substrate. In an embodiment, the BEOL stack comprises first interconnects and second interconnects in an interconnect layer of the BEOL stack. In an embodiment, the first interconnects have a first height and the second interconnects have a second height that is different than the first height.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Mark ANDERS, Himanshu KAUL, Ram KRISHNAMURTHY, Kevin Lai LIN, Mauro KOBRINSKY
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Publication number: 20210043500Abstract: Embodiments disclosed herein include interconnect layers that include non-uniform interconnect heights and methods of forming such devices. In an embodiment, an interconnect layer comprises an interlayer dielectric (ILD), a first interconnect disposed in the ILD, wherein the first interconnect has a first height, and a second interconnect disposed in the ILD, wherein the second interconnect has a second height that is different than the first height.Type: ApplicationFiled: August 7, 2019Publication date: February 11, 2021Inventors: Kevin Lai LIN, Mauro KOBRINSKY, Mark ANDERS, Himanshu KAUL, Ram KRISHNAMURTHY
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Publication number: 20200388753Abstract: Embodiments disclosed herein include memory bitcells and methods of forming such memory bitcells. In an embodiment, the memory bitcell is part of an embedded DRAM (eDRAM) memory device. In an embodiment, the memory bitcell comprises a substrate and a storage element embedded in the substrate. In an embodiment, the storage element comprises a phase changing material that comprises a binary alloy. In an embodiment, the memory bitcell further comprises a first electrode over a first surface of the storage element, and a second electrode over a second surface of the storage element.Type: ApplicationFiled: June 10, 2019Publication date: December 10, 2020Inventors: Elijah KARPOV, Mauro KOBRINSKY
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Publication number: 20200303191Abstract: Embodiments herein describe techniques for bonded wafers that includes a first wafer bonded with a second wafer, and a stress compensation layer in contact with the first wafer or the second wafer. The first wafer has a first stress level at a first location, and a second stress level different from the first stress level at a second location. The stress compensation layer includes a first material at a first location of the stress compensation layer that induces a third stress level at the first location of the first wafer, a second material different from the first material at a second location of the stress compensation layer that induces a fourth stress level different from the third stress level at the second location of the first wafer. Other embodiments may be described and/or claimed.Type: ApplicationFiled: March 18, 2019Publication date: September 24, 2020Inventors: Anant JAHAGIRDAR, Chytra PAWASHE, Aaron LILAK, Myra MCDONNELL, Brennen MUELLER, Mauro KOBRINSKY
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Publication number: 20200194338Abstract: An example relates to an integrated circuit including a semiconductor substrate, and a wiring layer stack located on the semiconductor substrate. The integrated circuit further includes a transistor embedded in the wiring layer stack. The transistor includes an embedded layer. The embedded layer has a thickness of less than 10 nm. The embedded layer includes at least one two-dimensional crystalline layer including more than 10% metal atoms. Further examples relate to methods for forming integrated circuits.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek Sharma, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
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Publication number: 20200194376Abstract: An aspect of the disclosure relates to an integrated circuit. The integrated circuit includes a first electrically conductive structure, a thin film crystal layer located on the first electrically conductive structure, and a second electrically conductive structure including metal e.g. copper. The second electrically conductive structure is located on the thin film crystal layer. The first electrically conductive structure is electrically connected to the second electrically conductive structure through the thin film crystal layer. The thin film crystal layer may be provided as a copper diffusion barrier.Type: ApplicationFiled: December 17, 2018Publication date: June 18, 2020Inventors: Carl NAYLOR, Ashish AGRAWAL, Kevin LIN, Abhishek SHARMA, Mauro KOBRINSKY, Christopher JEZEWSKI, Urusa ALAAN
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Patent number: 10685949Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.Type: GrantFiled: March 6, 2017Date of Patent: June 16, 2020Assignee: Intel CorporationInventors: Aleksandar Aleksov, Mauro Kobrinsky, Johanna Swan, Rajendra C. Dias
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Publication number: 20190378790Abstract: Described herein are integrated circuit (IC) structures, devices, and methods associated with device layer interconnects. For example, an IC die may include a device layer including a transistor array along a semiconductor fin, and a device layer interconnect in the transistor array, wherein the device layer interconnect is in electrical contact with multiple different source/drain regions of the transistor array.Type: ApplicationFiled: June 7, 2018Publication date: December 12, 2019Applicant: Intel CorporationInventors: Mark Bohr, Mauro Kobrinsky, Marni Nabors
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Patent number: 10204855Abstract: Generally discussed herein are systems and methods that can include a stretchable and bendable device. According to an example a method can include (1) depositing a first elastomer material on a panel, (2) laminating trace material on the elastomer material, (3) processing the trace material to pattern the trace material into one or more traces and one or more bond pads, (4) attaching a die to the one or more bond pads, or (5) depositing a second elastomer material on and around the one or more traces, the bonds pads, and the die to encapsulate the one or more traces and the one or more bond pads in the first and second elastomer materials.Type: GrantFiled: July 11, 2014Date of Patent: February 12, 2019Assignee: Intel CorporationInventors: Alejandro Levander, Tatyana Andryushchenko, David Staines, Mauro Kobrinsky, Aleksandar Aleksov, Dilan Seneviratne, Javier Soto Gonzalez, Srinivas Pietambaram, Rafiqul Islam
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Publication number: 20170179103Abstract: Generally discussed herein are systems and apparatuses that can include apparatuses, systems, or method for a flexible, wire bonded device. According to an example an apparatus can include (1) a first rigid circuit comprising a first plurality of bond pads proximate to a first edge of the first rigid circuit, (2) a second rigid circuit comprising a second plurality of bond pads proximate to a first edge of the second rigid circuit, the second rigid circuit adjacent the first rigid circuit and the first edge of the second rigid circuit facing the first edge of the first rigid circuit, or (3) a first plurality of wire bonded wires, each wire bonded wire of the first plurality of wire bonded wires electrically and mechanically connected to a bond pad of the first plurality of bond pads and a bond pad of the second plurality of bond pads.Type: ApplicationFiled: March 6, 2017Publication date: June 22, 2017Inventors: Aleksandar Aleksov, Mauro Kobrinsky, Johanna Swan, Rajendra C. Dias