Patents by Inventor Maxime Darnon
Maxime Darnon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20130009312Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.Type: ApplicationFiled: September 4, 2012Publication date: January 10, 2013Applicant: International Business Machines CorporationInventors: Maxime Darnon, Jeffrey P. Gambino, Elbert E. Huang, Qinghuang Lin
-
Publication number: 20130001781Abstract: An interconnect structure is provided which includes at least one patterned and cured low-k material located directly on a surface of a substrate; and at least one least one conductively filled region embedded within an interconnect pattern located within the at least one patterned and cured low-k material, wherein the at least one conductively filled region has an inflection point at a lower region of the interconnect pattern that is in proximity to an upper surface of the substrate and the interconnect region having an upper region that has substantially straight sidewalls.Type: ApplicationFiled: September 1, 2012Publication date: January 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maxime Darnon, Qinghuang Lin
-
Publication number: 20120301980Abstract: The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nantotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nantobues are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.Type: ApplicationFiled: August 8, 2012Publication date: November 29, 2012Applicant: International Business Machines CorporationInventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Qinghuang Lin
-
Publication number: 20120280398Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: ApplicationFiled: July 3, 2012Publication date: November 8, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
-
Publication number: 20120276657Abstract: Embodiments of the invention generally relate to methods for fabricating devices on semiconductor substrates. More specifically, embodiments of the invention relate to methods of patterning magnetic materials. Certain embodiments described herein use a reducing chemistry containing a hydrogen gas or hydrogen containing gas with an optional dilution gas at temperatures ranging from 20 to 300 degrees Celsius at a substrate bias less than 1,000 DC voltage to reduce the amount of sputtering and redeposition. Exemplary hydrogen containing gases which may be used with the embodiments described herein include NH3, H2, CH4, C2H4, SiH4, and H2S. It has been found that patterning a magnetic tunnel junction with an oxidizer-free gas mixture comprising hydrogen maintains the integrity of the magnetic tunnel junction without producing harmful conductive residue.Type: ApplicationFiled: April 27, 2011Publication date: November 1, 2012Inventors: Olivier Joubert, Benjamin Schwarz, Jérémy Gilbert Maurice Pereira, Kevin Menguelti, Erwine Maude Pargon, Maxime Darnon
-
Patent number: 8298937Abstract: An interconnect structure within a microelectronic structure and a method for fabricating the interconnect structure within the microelectronic structure use a developable bottom anti-reflective coating layer and at least one imageable inter-level dielectric layer located thereupon over a substrate that includes a base dielectric layer and a first conductor layer located and formed embedded within the base dielectric layer. Incident to use of the developable bottom anti-reflective coating layer and the at least one imageable inter-level dielectric layer, an aperture, such as but not limited to a dual damascene aperture, may be formed through the at least one imageable inter-level dielectric layer and the developable anti-reflective coating layer to expose a capping layer located and formed upon the first conductor layer, absent use of a dry plasma etch method when forming the interconnect structure within the microelectronic structure.Type: GrantFiled: June 12, 2009Date of Patent: October 30, 2012Assignee: International Business Machines CorporationInventors: Maxime Darnon, Jeffrey P. Gambino, Elbert E. Huang, Qinghuang Lin
-
Patent number: 8241992Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: GrantFiled: May 10, 2010Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
-
Patent number: 8183694Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.Type: GrantFiled: February 6, 2011Date of Patent: May 22, 2012Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satya V. Nitta
-
Publication number: 20110311825Abstract: The present disclosure relates to a method for selectively etching-back a polymer matrix to expose tips of carbon nanotubes comprising: a. growing carbon nanotubes on a conductive substrate; b. filling the gap around the carbon nanotubes with a polymeric fill matrix comprising at least one latent photoacid generator; and c. selectively etching-back the polymeric fill matrix to expose tips of the carbon nanotubes.Type: ApplicationFiled: June 22, 2010Publication date: December 22, 2011Applicant: International Business Machines Corp.Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Ryan M. Martin, Ying Zhang
-
Publication number: 20110311781Abstract: The present disclosure relates to a method of patterning a photosensitive material on a polymeric fill matrix comprising at least one latent photoacid generator; and a structure prepared according to said method. The method comprises: a. depositing a polymeric fill matrix comprising at least one latent photoacid generator; b. curing the polymeric fill matrix; c. depositing a layer of photosensitive material directly onto the cured polymeric fill matrix; and d. forming a pattern with at least one opening in the layer of photosensitive material with lithography.Type: ApplicationFiled: June 22, 2010Publication date: December 22, 2011Applicant: International Business Machines Corp.Inventors: Maxime Darnon, Pratik P. Joshi, Qinghuang Lin
-
Publication number: 20110309507Abstract: The present disclosure relates to a structure comprising 1. an electrically conductive substrate having carbon nanotubes grown thereon; 2. a cured polymeric fill matrix comprising at least one latent photoacid generator embedded around the carbon nanotubes but allowing tips of the carbon nanotubes to be exposed; 3. a layer of patterned and cured photosensitive dielectric material on the cured polymeric fill matrix, wherein tips of the carbon nanotubes are exposed within the patterns; and 4. an electrically conductive material filled into the interconnect pattern and in contact with the exposed tips of the carbon nanotubes; and to methods of making the structure and using the structure to measure the electrical characteristics of carbon nanotubes.Type: ApplicationFiled: June 22, 2010Publication date: December 22, 2011Applicant: International Business Machines Corp.Inventors: Maxime Darnon, Gerald W. Gibson, Pratik P. Joshi, Qinghuang Lin
-
Publication number: 20110272810Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: ApplicationFiled: May 10, 2010Publication date: November 10, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
-
Publication number: 20110260326Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps of different depths are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: ApplicationFiled: April 27, 2010Publication date: October 27, 2011Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Qinghuang Lin, Anthony D. Lisi, Satyanarayana V. Nitta
-
Publication number: 20110221062Abstract: Methods for producing air gap-containing metal-insulator interconnect structures for VLSI and ULSI devices using a photo-patternable low k material as well as the air gap-containing interconnect structure that is formed are disclosed. More particularly, the methods described herein provide interconnect structures built in a photo-patternable low k material in which air gaps are defined by photolithography in the photo-patternable low k material. In the methods of the present invention, no etch step is required to form the air gaps. Since no etch step is required in forming the air gaps within the photo-patternable low k material, the methods disclosed in this invention provide highly reliable interconnect structures.Type: ApplicationFiled: March 10, 2010Publication date: September 15, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Maxime Darnon, Satyanarayana V. Nitta, Anthony D. Lisi, Qinghuang Lin
-
Publication number: 20110121457Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.Type: ApplicationFiled: February 6, 2011Publication date: May 26, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satya V. Nitta
-
Publication number: 20110115094Abstract: A single damascene or dual damascene interconnect structure fabricated with a photo-patternable low-k dielectric (PPLK) which is cured after etching. This interconnect method prevents the PPLK damage and the tapering of the edges of the interconnect structure. In one embodiment, the method of the present invention includes depositing a photo-patternable low-k (PPLK) material atop an initial structure. The initial structure can include a dielectric cap, an antireflective coating (ARC), or a material stack including the same. The at least one PPLK material is patterned, creating a single damascene structure. For dual damascene structures, a second PPLK layer is coated and patterned. An etch process is performed to transfer the pattern for the PPLK material into at least a portion of the substrate, typically into the dielectric cap and/or ARC using processes known by those skilled in the art (typically fluorocarbon-based plasmas). A diffusion liner deposition can follow the etch process.Type: ApplicationFiled: November 16, 2009Publication date: May 19, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Maxime Darnon, Qinghuang Lin
-
Publication number: 20110108989Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.Type: ApplicationFiled: November 11, 2009Publication date: May 12, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawerence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satyanarayana V. Nitta
-
Patent number: 7939446Abstract: A process to produce an airgap on a substrate having a dielectric layer comprises defining lines by lithography where airgaps are required. The lines' dimensions are shrunk by a trimming process (isotropic etching). The tone of the patterns is reversed by applying a planarizing layer which is etched down to the top of the patterns. The photoresist is removed, leading to sub-lithographic trenches which are transferred into a cap layer and eventually into the dielectric between two metal lines. The exposed dielectric is eventually damaged, and is etched out, leading to airgaps between metal lines. The gap is sealed by the pinch-off occurring during the deposition of the subsequent dielectric.Type: GrantFiled: November 11, 2009Date of Patent: May 10, 2011Assignee: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satya V. Nitta
-
Publication number: 20110100420Abstract: An apparatus, system, and method are disclosed for a photovoltaic module, the photovoltaic module comprising a plurality of photovoltaic cells, a controllable infrared protection layer, and a protection switching means. The controllable infrared protection layer is for reducing the infrared radiation absorbed by the photovoltaic module, where the controllable infrared protection layer has a first state and a second state. When the infrared protection layer is in the first state the transmission of infrared radiation to the photovoltaic cells is higher than when the infrared protection layer is in the second state. The protection switching means is for switching the controllable infrared protection layer between the first state and the second state.Type: ApplicationFiled: September 21, 2010Publication date: May 5, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Timothy J. Dalton, Maxime Darnon, Rainer Krause, Gerd Pfeiffer, Kevin Prettyman, Carl J. Radens, Brian C. Sapp
-
Publication number: 20110020753Abstract: A method for reversing the tone of a lithographic image on a substrate comprises depositing a modifiable material on a substrate; applying a photolithographic material on the modifiable material: defining a removable patterned area in the photolithopgraphic material by photolithograpic means; removing the patterned area to produce an exposed region in the modifiable material that substantially conforms to the patterned area; producing a reacted modifiable material by increasing the etch resistance of the modifable material substantially throughout the exposed region so that the etch resistance of the exposed region comprises a region that substantially conforms to the exposed region; and removing the photoresist and the modifiable material to leave the reacted modifiable material and substrate.Type: ApplicationFiled: July 27, 2009Publication date: January 27, 2011Applicant: International Business Machines CorporationInventors: Lawrence A. Clevenger, Maxime Darnon, Anthony D. Lisi, Satya V. Nitta