Patents by Inventor Maximilian Roesch

Maximilian Roesch has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10510836
    Abstract: A semiconductor device includes a gate trench extending into a Si substrate, the gate trench including a gate electrode and a gate dielectric separating the gate electrode from the Si substrate. The semiconductor device further includes a body region in the Si substrate adjacent the gate trench, the body region including a channel region which extends along a sidewall of the gate trench, a source region in the Si substrate above the body region, a contact trench extending into the Si substrate and filled with an electrically conductive material which contacts the source region and a highly doped body contact region at a bottom of the contact trench, and a diffusion barrier structure extending along at least part of the channel region and disposed between the channel region and the highly doped body contact region. The diffusion barrier structure includes alternating layers of Si and oxygen-doped Si.
    Type: Grant
    Filed: August 8, 2018
    Date of Patent: December 17, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Robert Haase, Martin Poelzl, Maximilian Roesch, Sylvain Leomant, Andreas Meiser
  • Publication number: 20190280117
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Publication number: 20190229198
    Abstract: A semiconductor device includes a trench extending into a first main surface of a semiconductor substrate, and a gate electrode and a gate dielectric in the trench. The gate dielectric separates the gate electrode from the semiconductor substrate. A first region having a first conductivity type is formed in the semiconductor substrate at the first surface adjacent the trench. A second region having a second conductivity type is formed in the semiconductor substrate below the first region adjacent the trench. A third region having the first conductivity type is formed in the semiconductor substrate below the second region adjacent the trench. A contact opening in the semiconductor substrate extends into the second region. An electrically insulative spacer is disposed on sidewalls of the semiconductor substrate formed by the contact opening, and an electrically conductive material in the contact opening adjoins the electrically insulative spacer on the sidewalls.
    Type: Application
    Filed: January 23, 2018
    Publication date: July 25, 2019
    Inventors: Wei-Chun Huang, Martin Poelzl, Thomas Feil, Maximilian Roesch
  • Patent number: 10249723
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 10181511
    Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: January 15, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Martin Poelzl, Georg Ehrentraut, Franz Hirler, Maximilian Roesch
  • Patent number: 10068848
    Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: September 4, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
  • Publication number: 20180138278
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 9859385
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20170207309
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 20, 2017
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20170125345
    Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines includes a resistance section formed of a locally increased specific resistance relative to a specific resistance of adjacent semiconductor material or metal of the respective connection line. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.
    Type: Application
    Filed: January 12, 2017
    Publication date: May 4, 2017
    Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
  • Patent number: 9627520
    Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Christian Geissler, Oliver Blank, Maximilian Roesch
  • Patent number: 9614044
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body includes a load transistor part and a sensor transistor part. A first source region of the load transistor part and a second source region of the sensor transistor part are electrically separated from each other. A common gate electrode in a common gate trench extends into the semiconductor body from a first surface. A first part of the common gate trench is in the load transistor part, and a second part of the common gate trench is in the sensor transistor part. A field electrode in a field electrode trench extends into the semiconductor body from the first surface. A maximum dimension of the field electrode trench parallel to the first surface is smaller than a depth of the field electrode trench.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: April 4, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Michael Hutzler, Maximilian Roesch
  • Patent number: 9570553
    Abstract: A semiconductor chip has a semiconductor body with a bottom side and a top side arranged distant from the bottom side in a vertical direction, an active and a non-active transistor region, a drift region formed in the semiconductor body, a contact terminal for externally contacting the semiconductor chip, and a plurality of transistor cells formed in the semiconductor body. Each of the transistor cells has a first electrode. Each of a plurality of connection lines electrically connects another one of the first electrodes to the contact terminal pad at a connecting location of the respective connection line. Each of the connection lines has a resistance section that is formed of at least one of: a locally reduced cross-sectional area of the connection line section; and a locally increased specific resistance. Each of the connecting locations and each of the resistance sections is arranged in the non-active transistor region.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: February 14, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Gerhard Noebauer, Ralf Siemieniec, Maximilian Roesch, Martin Poelzl, Michael Hutzler
  • Patent number: 9543398
    Abstract: A semiconductor switching device includes a first load terminal electrically connected to source zones of transistor cells. The source zones form first pn junctions with body zones. A second load terminal is electrically connected to a drain construction that forms second pn junctions with the body zones. Control structures, which include a control electrode and charge storage structures, directly adjoin the body zones. The control electrode controls a load current through the body zones. The charge storage structures insulate the control electrode from the body zones and contain a control charge adapted to induce inversion channels in the body zones in the absence of a potential difference between the control electrode and the first load electrode.
    Type: Grant
    Filed: July 31, 2015
    Date of Patent: January 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Johannes Georg Laven, Anton Mauder, Matteo Dainese, Franz Hirler, Christian Jaeger, Maximilian Roesch, Wolfgang Roesner, Martin Stiftinger, Robert Strenz
  • Patent number: 9484410
    Abstract: A semiconductor component may include a semiconductor layer which has a front side and a back side, a first terminal electrode on the front side, a second terminal electrode on the back side, a first dopant region of a first conduction type on the front side, which is electrically connected to one of the terminal electrodes, a second dopant region of a second conduction type in the semiconductor layer, which is electrically connected to the other terminal electrode, a pn junction being formed between the first and second dopant regions, a dielectric layer on the back side between the semiconductor layer and the second terminal electrode, and the dielectric layer having an opening through which an electrical connection between the second terminal electrode and the first or second dopant region is passed.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: November 1, 2016
    Assignee: Infineon Technologies AG
    Inventors: Oliver Haeberlen, Franz Hirler, Maximilian Roesch
  • Publication number: 20160225884
    Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
    Type: Application
    Filed: January 28, 2016
    Publication date: August 4, 2016
    Applicant: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Christian Geissler, Oliver Blank, Maximilian Roesch
  • Publication number: 20160111504
    Abstract: First trenches extend from a process surface into a semiconductor layer. An alignment layer with mask pits in a with respect to the process surface vertical projection of the first trenches is formed on the process surface. Sidewalls of the mask pits have a smaller tilt angle with respect to the process surface than sidewalls of the first trenches. The mask pits are filled with an auxiliary material. A gate trench for a gate structure is formed in a mesa section of the semiconductor layer between the first trenches, wherein the auxiliary material is used as an etch mask.
    Type: Application
    Filed: October 13, 2015
    Publication date: April 21, 2016
    Inventors: Martin Poelzl, Oliver Blank, Franz Hirler, Maximilian Roesch, Li Juin Yip
  • Publication number: 20160104797
    Abstract: A semiconductor device comprises a gate electrode in a trench in a semiconductor body. The gate electrode comprises a plurality of gate segments disposed along an extension direction of the trench, the gate segments being connected to neighboring gate segments by means of connection elements. A distance between adjacent gate segments is equal to or smaller than 0.5*L, wherein L denotes a length of each of the gate segments, the length being measured along the extension direction of the trench.
    Type: Application
    Filed: September 30, 2015
    Publication date: April 14, 2016
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Martin Poelzl, Georg Ehrentraut, Franz Hirler, Maximilian Roesch
  • Publication number: 20160079377
    Abstract: A semiconductor device includes a semiconductor body. The semiconductor body includes a load transistor part and a sensor transistor part. A first source region of the load transistor part and a second source region of the sensor transistor part are electrically separated from each other. A common gate electrode in a common gate trench extends into the semiconductor body from a first surface. A first part of the common gate trench is in the load transistor part, and a second part of the common gate trench is in the sensor transistor part. A field electrode in a field electrode trench extends into the semiconductor body from the first surface. A maximum dimension of the field electrode trench parallel to the first surface is smaller than a depth of the field electrode trench.
    Type: Application
    Filed: September 14, 2015
    Publication date: March 17, 2016
    Inventors: Michael Hutzler, Maximilian Roesch
  • Patent number: 9252251
    Abstract: A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.
    Type: Grant
    Filed: December 19, 2011
    Date of Patent: February 2, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Franz Hirler, Ralf Siemieniec, Christian Geissler, Oliver Blank, Maximilian Roesch