Patents by Inventor Mayank Bulsara

Mayank Bulsara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacture of a semiconductor on insulator structure
    Patent number: 10796946
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: October 6, 2020
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • METHOD OF MANUFACTURE OF A SEMICONDUCTOR ON INSULATOR STRUCTURE
    Publication number: 20200035544
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Application
    Filed: October 7, 2019
    Publication date: January 30, 2020
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Method of manufacture of a semiconductor on insulator structure
    Patent number: 10475696
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: November 12, 2019
    Assignee: SunEdison Semiconductor Limited (UEN201334164H)
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • METHOD OF MANUFACTURE OF A SEMICONDUCTOR ON INSULATOR STRUCTURE
    Publication number: 20190019721
    Abstract: A method is provided for preparing a semiconductor-on-insulator structure comprising a multilayer dielectric layer.
    Type: Application
    Filed: June 6, 2018
    Publication date: January 17, 2019
    Inventors: Henry Frank Erk, Sasha Kweskin, Jeffrey L. Libbert, Mayank Bulsara
  • Methods for Forming Strained Channel Dynamic Random Access Memory Devices
    Publication number: 20120302032
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: August 7, 2012
    Publication date: November 29, 2012
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Strained channel dynamic random access memory devices
    Patent number: 8253181
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: July 3, 2008
    Date of Patent: August 28, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
    Patent number: 7594967
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Grant
    Filed: October 10, 2002
    Date of Patent: September 29, 2009
    Assignee: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Strained channel dynamic random access memory devices
    Publication number: 20080265299
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 30, 2008
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Methods of forming dynamic random access memory trench capacitors
    Patent number: 7410861
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: October 15, 2004
    Date of Patent: August 12, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Dynamic random access memory trench capacitors
    Patent number: 7408214
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: August 5, 2008
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Methods for Selective Placement of Dislocation Arrays
    Publication number: 20080070397
    Abstract: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.
    Type: Application
    Filed: November 26, 2007
    Publication date: March 20, 2008
    Inventors: Anthony Lochtefeld, Christopher Leitz, Matthew Currie, Mayank Bulsara
  • Method of forming multiple gate insulators on a strained semiconductor heterostructure
    Patent number: 7172935
    Abstract: A method for forming multiple gate insulators on a strained semiconductor heterostructure, including the steps of oxidation and deposition.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: February 6, 2007
    Assignee: AmberWave Systems Corporation
    Inventors: Anthony Lochtefeld, Mayank Bulsara
  • Method of forming multiple gate insulators on a strained semiconductor heterostructure
    Publication number: 20050098774
    Abstract: A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.
    Type: Application
    Filed: December 17, 2004
    Publication date: May 12, 2005
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony Lochtefeld, Mayank Bulsara
  • Dynamic random access memory trench capacitors
    Patent number: 6891209
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: May 10, 2005
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew T. Currie, Anthony J. Lochtefeld
  • Methods of forming dynamic random access memory trench capacitors
    Publication number: 20050067647
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: October 15, 2004
    Publication date: March 31, 2005
    Applicant: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew Currie, Anthony Lochtefeld
  • Dynamic random access memory trench capacitors
    Publication number: 20050035389
    Abstract: DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined.
    Type: Application
    Filed: September 23, 2004
    Publication date: February 17, 2005
    Applicant: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Matthew Currie, Anthony Lochtefeld
  • Method of forming multiple gate insulators on a strained semiconductor heterostructure
    Patent number: 6849508
    Abstract: A method is disclosed for forming multiple gate insulators on a strained semiconductor heterostructure as well as the devices and circuits formed therefrom. In an embodiment, the method includes the steps of depositing a first insulators on the strained semiconductor heterostructure, removing at least a portion of the first insulators from the strained semiconductor heterostructure, and depositing a second insulators on the strained semiconductor heterostructure.
    Type: Grant
    Filed: June 7, 2002
    Date of Patent: February 1, 2005
    Assignee: AmberWave Systems Corporation
    Inventors: Anthony Lochtefeld, Mayank Bulsara
  • Selective placement of dislocation arrays
    Publication number: 20040115916
    Abstract: Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation arrays with respect to devices subsequently formed on the layers.
    Type: Application
    Filed: July 29, 2003
    Publication date: June 17, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Anthony J. Lochtefeld, Christopher W. Leitz, Matthew T. Currie, Mayank Bulsara
  • Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
    Publication number: 20040040493
    Abstract: A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects.
    Type: Application
    Filed: October 10, 2002
    Publication date: March 4, 2004
    Applicant: AmberWave Systems Corporation
    Inventors: Christopher J. Vineis, Richard Westhoff, Mayank Bulsara
  • Relaxed InxGa1-xAs layers integrated with Si
    Patent number: 6594293
    Abstract: A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxailly growing a relaxed graded layer of InxGal-xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: July 15, 2003
    Assignee: AmberWave Systems Corporation
    Inventors: Mayank Bulsara, Eugene A. Fitzgerald