Patents by Inventor Mayank Garg

Mayank Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120625
    Abstract: A wearable biosensor for real-time quantification of a biomarker in a biofluid includes at least one functional module. The functional module includes an iontophoresis induction module, a microfluidic layer, a plurality of multimodal biosensors, and a paperfluidic layer.
    Type: Application
    Filed: October 12, 2024
    Publication date: April 17, 2025
    Applicant: The Texas A&M University System
    Inventors: Limei Tian, Mayank Garg
  • Patent number: 12242695
    Abstract: In some examples, an electronic device including a touch screen can sense a stylus proximate to the touch screen. For example, the user can draw or write with the stylus to create a simulated drawing or simulated handwriting displayed on the touch screen. In some examples, the electronic device can sense a series of “points” corresponding to the location of the stylus over time while the drawing/writing input was provided. In some situations, noise in the stylus data can cause the electronic device not to sense one or more noisy points included in the drawing or handwriting input. In some examples, the electronic device can interpolate the noisy points based on sensed points before and/or after the time of the skipped points.
    Type: Grant
    Filed: September 6, 2023
    Date of Patent: March 4, 2025
    Assignee: Apple Inc.
    Inventors: Thomas Deselaers, Peder Blekken, Francisco Alvaro Munoz, Ryan S. Dixon, Nima Ferdosi, Tianchang Gu, Mayank Garg
  • Publication number: 20240396554
    Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
    Type: Application
    Filed: August 2, 2024
    Publication date: November 28, 2024
    Inventors: Win Naing Maung, Bharath Kumar Singareddy, Soumi Paul, Mayank Garg, Suzanne Mary Vining
  • Patent number: 12088293
    Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: September 10, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Win Naing Maung, Bharath Kumar Singareddy, Soumi Paul, Mayank Garg, Suzanne Mary Vining
  • Publication number: 20240250715
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Application
    Filed: April 3, 2024
    Publication date: July 25, 2024
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Patent number: 12001636
    Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: June 4, 2024
    Assignee: APPLE INC.
    Inventors: Guangtao Zhang, Apexit Shah, Heemin Yang, Kevin D. Spratt, Mayank Garg, Nima Ferdosi, Vikram Garg, William J. Esposito, Tavys Q. Ashcroft
  • Patent number: 11984941
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Grant
    Filed: January 23, 2023
    Date of Patent: May 14, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Publication number: 20240002310
    Abstract: An energetic composition and a method of unzipping polymer binders are disclosed, which includes localizing a heat feedback just near the reaction front by unzipping polymer binders employed to a nanothermite. The energetic composition includes an unzipping polymer binder employed to high load fuel and oxidizer particles.
    Type: Application
    Filed: June 28, 2023
    Publication date: January 4, 2024
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, The Board of Trustees of the University of Illinois
    Inventors: Haiyang Wang, Michael R. Zachariah, Jeffrey S. Moore, Mayank Garg
  • Publication number: 20230367433
    Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Guangtao Zhang, Apexit Shah, Heemin Yang, Kevin D. Spratt, Mayank Garg, Nima Ferdosi, Vikram Garg, William J. Esposito, Tavys Q. Ashcroft
  • Patent number: 11762508
    Abstract: Grip detection can be beneficial for an electronic device to ignore unintended contacts on a touch sensitive surface. Examples of the disclosure provide various ways for identifying an input patch as a grip. In some examples, identifying an input patch as a grip comprises determining whether the input patch satisfies one or more grip identification criteria. In some examples, identified grips are saved in a grip database. In some examples, the identified grips are filtered out of touch images. In some examples, when baseline touch data for a touch-sensitive is updated, the touch processor can forgo updating the baseline for portions of the touch sensitive surface associated with the identified grips.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: September 19, 2023
    Assignee: Apple Inc.
    Inventors: Mayank Garg, Apexit Shah
  • Patent number: 11755154
    Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: September 12, 2023
    Assignee: APPLE INC.
    Inventors: Guangtao Zhang, Apexit Shah, Heemin Yang, Kevin D. Spratt, Mayank Garg, Nima Ferdosi, Vikram Garg, William J. Esposito, Tavys Q. Ashcroft
  • Publication number: 20230280868
    Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.
    Type: Application
    Filed: March 3, 2022
    Publication date: September 7, 2023
    Inventors: Guangtao Zhang, Apexit Shah, Heemin Yang, Kevin D. Spratt, Mayank Garg, Nima Ferdosi, Vikram Garg, William J. Esposito, Tavys Q. Ashcroft
  • Patent number: 11669069
    Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.
    Type: Grant
    Filed: June 4, 2021
    Date of Patent: June 6, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Matthew David Romig, Mayank Garg
  • Publication number: 20230155628
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Application
    Filed: January 23, 2023
    Publication date: May 18, 2023
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Patent number: 11630797
    Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.
    Type: Grant
    Filed: June 7, 2021
    Date of Patent: April 18, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Anant Shankar Kamath, Rakesh Hariharan, Vivekkumar Ramanlal Vadodariya, Soumi Paul, Mayank Garg
  • Publication number: 20230028275
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Application
    Filed: July 22, 2021
    Publication date: January 26, 2023
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Patent number: 11563462
    Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.
    Type: Grant
    Filed: July 22, 2021
    Date of Patent: January 24, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Srijan Rastogi, Mayank Garg, Anant Shankar Kamath
  • Patent number: 11556492
    Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.
    Type: Grant
    Filed: June 30, 2021
    Date of Patent: January 17, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ganapathi Hegde, Krushal Shah, Mayank Garg, Luis Eduardo Ossa, Vashist Bist
  • Publication number: 20230004516
    Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.
    Type: Application
    Filed: June 30, 2021
    Publication date: January 5, 2023
    Inventors: Ganapathi HEGDE, Krushal SHAH, Mayank GARG, Luis Eduardo OSSA, Vashist BIST
  • Patent number: 11528026
    Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.
    Type: Grant
    Filed: October 28, 2020
    Date of Patent: December 13, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Mayank Garg, Shu-Ing Ju, Arun Rao, Wei Zhang