Patents by Inventor Mayank Shrivastava

Mayank Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11829855
    Abstract: Training query intents are allocated for multiple training entities into training time intervals in a time series based on a corresponding query intent time for each training query intent. Training performance results for the multiple training entities are allocated into the training time intervals in the time series based on a corresponding performance time of each training performance result. A machine learning model for a training milestone of the time series is trained based on the training query intents allocated to a training time interval prior to the training milestone and the training performance results allocated to a training time interval after the training milestone. Target performance for the target entity for an interval after a target milestone in the time series is predicted by inputting to the trained machine learning model target query intents allocated to the target entity in a target time interval before the target milestone.
    Type: Grant
    Filed: May 25, 2022
    Date of Patent: November 28, 2023
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mayank Shrivastava, Hui Zhou, Pushpraj Shukla, Emre Hamit Kok, Sonal Prakash Mane, Dimitrios Brisimitzis
  • Patent number: 11522078
    Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.
    Type: Grant
    Filed: July 6, 2018
    Date of Patent: December 6, 2022
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Rohith Soman, Ankit Soni, Mayank Shrivastava, Srinivasan Raghavan, Navakant Bhat
  • Publication number: 20220284350
    Abstract: Training query intents are allocated for multiple training entities into training time intervals in a time series based on a corresponding query intent time for each training query intent. Training performance results for the multiple training entities are allocated into the training time intervals in the time series based on a corresponding performance time of each training performance result. A machine learning model for a training milestone of the time series is trained based on the training query intents allocated to a training time interval prior to the training milestone and the training performance results allocated to a training time interval after the training milestone. Target performance for the target entity for an interval after a target milestone in the time series is predicted by inputting to the trained machine learning model target query intents allocated to the target entity in a target time interval before the target milestone.
    Type: Application
    Filed: May 25, 2022
    Publication date: September 8, 2022
    Inventors: Mayank SHRIVASTAVA, Hui ZHOU, Pushpraj SHUKLA, Emre Hamit KOK, Sonal Prakash MANE, Dimitrios BRISIMITZIS
  • Patent number: 11393923
    Abstract: A Drain Extended Tunnel FET (DeTFET) device is disclosed that outperforms state of art devices and can meet the requirements of High voltage/high power devices operating in the range of 5V-20V for System on Chip (SoC). The device comprises a P+ SiGe source with an N-type Si Epilayer sandwiched between SiGe source and the gate stack, which enables vertical tunneling of minority carriers from SiGe P+ source into N-Epi region under the influence of gate field. The area tunneling between SiGe source and Si Epi region breaks the barrier imposed by thermionic injection based carrier transport from source to channel, which exists in DeMOS devices known in the art. The disclosed device results in improved performance in respect of ON current, leakage, sub-threshold slope, breakdown voltage and RF characteristics making it attractive for SoC applications as compared to its state of the art counterparts.
    Type: Grant
    Filed: February 23, 2017
    Date of Patent: July 19, 2022
    Assignee: Indian Institute of Science
    Inventor: Mayank Shrivastava
  • Patent number: 11361244
    Abstract: Training query intents are allocated for multiple training entities into training time intervals in a time series based on a corresponding query intent time for each training query intent. Training performance results for the multiple training entities are allocated into the training time intervals in the time series based on a corresponding performance time of each training performance result. A machine learning model for a training milestone of the time series is trained based on the training query intents allocated to a training time interval prior to the training milestone and the training performance results allocated to a training time interval after the training milestone. Target performance for the target entity for an interval after a target milestone in the time series is predicted by inputting to the trained machine learning model target query intents allocated to the target entity in a target time interval before the target milestone.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: June 14, 2022
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Mayank Shrivastava, Hui Zhou, Pushpraj Shukla, Emre Hamit Kok, Sonal Prakash Mane, Dimitrios Brisimitzis
  • Publication number: 20210365965
    Abstract: The disclosure herein describes a system for generating embeddings representing sequential human activity by self-supervised, deep learning models capable of being utilized by a variety of machine learning prediction models to create predictions and recommendations. An encoder-decoder is provided to create user-specific journeys, including sequenced events, based on human activity data from a plurality of tables, a customer data platform, or other sources. Events are represented by sequential feature vectors. A user-specific embedding representing user activities in relationship to activities of one or more other users is created for each user in a plurality of users. The embeddings are updated in real-time as new activity data is received. The embeddings can be fine-tuned using labeled data to customize the embeddings for a specific predictive model.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 25, 2021
    Inventors: Mayank SHRIVASTAVA, Sagar GOYAL, Sahil BHATNAGAR, Pin-Jung CHEN, Pushpraj SHUKLA, Arko P. MUKHERJEE
  • Patent number: 11157539
    Abstract: A computing system including one or more processors generates a topic set for a domain. A taxonomic evaluator is executed by the one or more processors to evaluate a set of category clusters generated from domain-specific textual data against a domain-specific taxonomic tree based on a coherency condition and to identify the category clusters that satisfy the coherency condition. The domain-specific taxonomic tree is generated from hierarchical structures of documents relating to the domain. Each identified category cluster is labeled with a label. A topic set creator is executed by the one or more processors to insert the labels of the set of identified category clusters into the topic set for the domain.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: October 26, 2021
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Chhaya Methani, Mayank Shrivastava, Pushpraj Shukla, Jonas Barklund, Dario Vignudelli, Ipolitas Clinton Dunaravich, Hung-An Chang
  • Patent number: 11086710
    Abstract: A method, system and computer program product includes receiving data including parameters affecting recovery point objectives for a disaster recovery plan, analyzing the parameters and determining responsible factors behind recovery point objective deviation based on the analyzing.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 10, 2021
    Assignee: International Business Machines Corporation
    Inventors: Ravi Kumar Raghunathan, Sukumar Madawat, Kajol Jain, Prabhleen Kaur, Mayank Shrivastava
  • Publication number: 20210173874
    Abstract: In some examples, feature and context based search result generation may include identifying, based on analysis of a query feature associated with a query context of a query, and an entity feature associated with an entity context of each entity of a plurality of entities, a reduced number of entities that match the query. Based on analysis of a further query feature and a further entity feature, further matching analysis of the query to the reduced number of entities may be performed. The query may be linked by a linking model to an entity of the reduced number of entities to generate a query and entity pair. Selection of an entity may be received, and a linked plurality of queries and entities may be searched. In this regard, search results may be generated and include a set of queries that is associated with the selected entity.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 10, 2021
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Allison Giddings, Mo Zhou, Dong Yuan, Tao Li, Mayank Shrivastava, Emre Kok, Hui Zhou
  • Patent number: 11031493
    Abstract: The present invention proposes a set of impurity doping configurations for GaN buffer in an AlGaN/GaN HEMT device to improve breakdown characteristics of the device. The breakdown characteristics depend on a unique mix of donor and acceptor traps and using carbon as a dopant increases both donor and acceptor trap concentrations, resulting in a trade-off in breakdown voltage improvement and device performance. A modified silicon and carbon co-doping is proposed, which enables independent control over donor and acceptor trap concentrations in the buffer, thus potentially improving breakdown characteristics of the device without adversely affecting the device performance.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 8, 2021
    Inventors: Mayank Shrivastava, Vipin Joshi
  • Publication number: 20210119044
    Abstract: A Drain Extended Tunnel FET (DeTFET) device is disclosed that outperforms state of art devices and can meet the requirements of High voltage/high power devices operating in the range of 5V-20V for System on Chip (SoC). The device comprises a P+ SiGe source with an N-type Si Epilayer sandwiched between SiGe source and the gate stack, which enables vertical tunneling of minority carriers from SiGe P+ source into N-Epi region under the influence of gate field. The area tunneling between SiGe source and Si Epi region breaks the barrier imposed by thermionic injection based carrier transport from source to channel, which exists in DeMOS devices known in the art. The disclosed device results in improved performance in respect of ON current, leakage, sub-threshold slope, breakdown voltage and RF characteristics making it attractive for SoC applications as compared to its state of the art counterparts.
    Type: Application
    Filed: February 23, 2017
    Publication date: April 22, 2021
    Applicant: Indian Institute of Science
    Inventor: Mayank SHRIVASTAVA
  • Publication number: 20210034448
    Abstract: A method, system and computer program product includes receiving data including parameters affecting recovery point objectives for a disaster recovery plan, analyzing the parameters and determining responsible factors behind recovery point objective deviation based on the analyzing.
    Type: Application
    Filed: July 29, 2019
    Publication date: February 4, 2021
    Inventors: Ravi Kumar Raghunathan, Sukumar Madawat, Kajol Jain, Prabhleen Kaur, Mayank Shrivastava
  • Patent number: 10840348
    Abstract: The present disclosure provides an improved enhancement mode field effect transistor (FET) having an oxide (AlxTi1-xO) emulating p-type gate. The present disclosure provides a novel enhancement mode High Electron Mobility Transistor (HEMT) structure with AlxTi1-xO Gate Oxide Engineering as Replacement of p-GaN Gate. In an aspect, the present disclosure provides a hybrid gate stack that combines p-GaN technology with the proposed oxide for e-mode operation. The HEMT structure with AlxTi1-xO Gate oxide provides a threshold voltage tuning from negative to positive by changing p-doping composition. Using a developed p-type oxide, e-mode device shows ON current ˜400 mA/mm, sub-threshold slope of 73 mV/dec, Ron=8.9 ?mm, interface trap density <1010 mm?2eV?1 and gate leakage below 200 nA/mm at the OFF-state breakdown.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: November 17, 2020
    Assignee: Indian Institute of Science
    Inventors: Mayank Shrivastava, Sayak Dutta Gupta, Ankit Soni, Srinivasan Raghavan, Navakanta Bhat
  • Publication number: 20200227543
    Abstract: A High Electron Mobility Transistor (HEMT) having a reduced surface field (RESURF) junction is provided. The HEMT includes a source electrode at a first end and a drain electrode at a second end. A gate electrode is provided between the source electrode and the drain electrode. A reduced surface field (RESURF) junction extends from the first end to the second end. The gate electrode is provided above the RESURF junction. A buried channel layer is formed in the RESURF junction on application of a positive voltage at the gate electrode. The RESURF junction includes an n-type Gallium nitride (GaN) layer and a p-type GaN layer. The n-type GaN layer is provided between the p-type GaN layer and the gate electrode.
    Type: Application
    Filed: July 6, 2018
    Publication date: July 16, 2020
    Inventors: Rohith SOMAN, Ankit SONI, Mayank SHRIVASTAVA, Srinivasan RAGHAVAN, Navakant BHAT
  • Patent number: 10671931
    Abstract: A multi-horizon predictor system that predicts a future parameter value for multiple horizons based on time-series data of the parameter, external data, and machine-learning. For a given time horizon, a time series data splitter splits the time into training data corresponding to a training time period, and a validation time period corresponding to a validation time period between the training time period and the given horizon. A model tuner tunes the prediction model of the given horizon fitting an initial prediction model to the parameter using the training data thereby using machine learning. The model tuner also tunes the initial prediction model by adjusting an effect of the external data on the prediction to generate a final prediction model for the given horizon using the validation data. A multi-horizon predictor causes the time series data splitter and the model tuner to operate for each of multiple horizons.
    Type: Grant
    Filed: June 9, 2016
    Date of Patent: June 2, 2020
    Assignee: MICROSOFT TECHNOLOGY LICENSING, LLC
    Inventors: Gagan Bansal, Amita Surendra Gajewar, Debraj GuhaThakurta, Konstantin Golyaev, Mayank Shrivastava, Vijay Krishna Narayanan, Walter Sun
  • Patent number: 10629586
    Abstract: The present disclosure relates to a Dual Fin SCR device having two parallel fins on which cathode, anode, n- and p-type triggering taps are selectively doped, wherein one Fin (or group of parallel Fins) comprises anode and n-tap, and other Fin (or group of parallel Fins) comprises cathode and p-tap. As key regions of the proposed SCR (anode and cathode), which carry majority of current after triggering, are placed diagonally, they provide substantial benefit in terms of spreading current and dissipating heat. The proposed SCR ESD protection device helps obtain regenerative feedback between base-collector junctions of two back-to-back bipolar transistors, which enables the proposed SCR to shunt ESD current. The proposed SCR design enables lower trigger and holding voltage for efficient and robust ESD protection. The proposed SCR device/design helps offer a tunable trigger voltage and a holding voltage with highfailure threshold.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: April 21, 2020
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Milova Paul, Mayank Shrivastava, B. Sampath Kumar, Christian Russ, Harald Gossner
  • Patent number: 10553712
    Abstract: The present disclosure provides a superjunction based design for normally-OFF HEMT that has two key components: (i) a recessed high-K metal gate and (ii) a superjunction layer under the gate, which is embedded within the N-type GaN buffer layers and separated from recessed gate. Recess gate is to deplete the 2 DEG from the channel region (under the gate) when the transistor is under OFF state. The present disclosure provides a new, improved, efficient and technically advanced HEMT device which can provide higher breakdown voltage, when compared to designs available in the prior-art, without affecting the performance figure of merits. Further, the new HEMT device offers improved breakdown voltage as compared to ON-resistance trade-off, improved the short channel effects, improved gate control over channel, improved switching speed for a given breakdown voltage, and improved device reliability. Furthermore, the new HEMT device lowers gate-to-drain (miller) capacitance and is available at low cost.
    Type: Grant
    Filed: July 11, 2018
    Date of Patent: February 4, 2020
    Assignee: INDIAN INSTITUTE OF TECHNOLOGY
    Inventor: Mayank Shrivastava
  • Patent number: 10535762
    Abstract: SCRs are a must for ESD protection in low voltage—high speed I/O as well as ESD protection of RF pads due to least parasitic loading and smallest foot print offered by SCRs. However, conventionally designed SCRs in FinFET and Nanowire technology suffer from very high turn-on and holding voltage. This issue becomes more severe in sub-14 nm non-planar technologies and cannot be handled by conventional approaches like diode- or transient-turn-on techniques. Proposed invention discloses SCR concept for FinFET and Nanowire technology with diffused junction profiles with sub-3V trigger and holding voltage for efficient and robust ESD protection. Besides low trigger and holding voltage, the proposed device offers a 3 times better ESD robustness per unit area.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: January 14, 2020
    Assignee: INDIAN INSTITUTE OF SCIENCE
    Inventors: Mayank Shrivastava, Milova Paul, Harald Gossner
  • Publication number: 20190392078
    Abstract: A computing system including one or more processors generates a topic set for a domain. A taxonomic evaluator is executed by the one or more processors to evaluate a set of category clusters generated from domain-specific textual data against a domain-specific taxonomic tree based on a coherency condition and to identify the category clusters that satisfy the coherency condition. The domain-specific taxonomic tree is generated from hierarchical structures of documents relating to the domain. Each identified category cluster is labeled with a label. A topic set creator is executed by the one or more processors to insert the labels of the set of identified category clusters into the topic set for the domain.
    Type: Application
    Filed: June 22, 2018
    Publication date: December 26, 2019
    Inventors: Chhaya METHANI, Mayank SHRIVASTAVA, Pushpraj SHUKLA, Jonas BARKLUND, Dario VIGNUDELLI, Ipolitas Clinton DUNARAVICH, Hung-An CHANG
  • Publication number: 20190378048
    Abstract: Training query intents are allocated for multiple training entities into training time intervals in a time series based on a corresponding query intent time for each training query intent. Training performance results for the multiple training entities are allocated into the training time intervals in the time series based on a corresponding performance time of each training performance result. A machine learning model for a training milestone of the time series is trained based on the training query intents allocated to a training time interval prior to the training milestone and the training performance results allocated to a training time interval after the training milestone. Target performance for the target entity for an interval after a target milestone in the time series is predicted by inputting to the trained machine learning model target query intents allocated to the target entity in a target time interval before the target milestone.
    Type: Application
    Filed: June 8, 2018
    Publication date: December 12, 2019
    Inventors: Mayank SHRIVASTAVA, Hui ZHOU, Pushpraj SHUKLA, Emre Hamit KOK, Sonal Prakash MANE, Dimitrios BRISIMITZIS