Patents by Inventor Mayank Shrivastava
Mayank Shrivastava has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9356013Abstract: A semiconductor device including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type adjacent to the first region; third and fourth semiconductor regions of the second conductivity type over or at least partially within the first semiconductor region; a fifth semiconductor region of the first conductivity type between the third and fourth semiconductor regions; a first gate over the fifth semiconductor region; sixth and seventh semiconductor regions of the first conductivity type over or at least partially within the second semiconductor region; an eighth semiconductor region of the second conductivity type between the sixth and seventh semiconductor regions; a second gate over the eighth semiconductor region; the third and seventh semiconductor regions coupled to first and second regions of the first gate, respectively, and the fourth and sixth semiconductor regions coupled to first and second regions of the second gate, respectively.Type: GrantFiled: July 5, 2013Date of Patent: May 31, 2016Assignee: Intel IP CorporationInventors: Mayank Shrivastava, Christian Russ
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Publication number: 20150340442Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.Type: ApplicationFiled: June 18, 2015Publication date: November 26, 2015Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
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Publication number: 20150255450Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.Type: ApplicationFiled: May 14, 2015Publication date: September 10, 2015Inventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
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Patent number: 9087892Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.Type: GrantFiled: September 16, 2013Date of Patent: July 21, 2015Assignee: Infineon Technologies AGInventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
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Publication number: 20150144997Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.Type: ApplicationFiled: February 5, 2015Publication date: May 28, 2015Inventors: Mayank Shrivastava, Christian Russ, Harald Gossner
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Patent number: 9035375Abstract: Embodiments relate to a field-effect device that includes a body region, a first source/drain region of a first conductivity type, a second source/drain region, and a pocket implant region adjacent to the first source/drain region, the pocket implant region being of a second conductivity type, wherein the second conductivity type is different from the first conductivity type. The body region physically contacts the pocket implant region.Type: GrantFiled: January 11, 2013Date of Patent: May 19, 2015Assignee: Infineon Technologies AGInventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
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Patent number: 8963201Abstract: One embodiment of the present invention relates to a silicon-controlled-rectifier (SCR). The SCR includes a longitudinal silicon fin extending between an anode and a cathode and including a junction region there between. One or more first transverse fins traverses the longitudinal fin at one or more respective tapping points positioned between the anode and the junction region. Other devices and methods are also disclosed.Type: GrantFiled: March 5, 2012Date of Patent: February 24, 2015Assignee: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Christian Russ, Harald Gossner
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Publication number: 20150008476Abstract: A semiconductor device including: a first semiconductor region of a first conductivity type; a second semiconductor region of a second conductivity type adjacent to the first region; third and fourth semiconductor regions of the second conductivity type over or at least partially within the first semiconductor region; a fifth semiconductor region of the first conductivity type between the third and fourth semiconductor regions; a first gate over the fifth semiconductor region; sixth and seventh semiconductor regions of the first conductivity type over or at least partially within the second semiconductor region; an eighth semiconductor region of the second conductivity type between the sixth and seventh semiconductor regions; a second gate over the eighth semiconductor region; the third and seventh semiconductor regions coupled to first and second regions of the first gate, respectively, and the fourth and sixth semiconductor regions coupled to first and second regions of the second gate, respectively.Type: ApplicationFiled: July 5, 2013Publication date: January 8, 2015Inventors: Mayank Shrivastava, Christian Russ
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Patent number: 8785968Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.Type: GrantFiled: October 8, 2012Date of Patent: July 22, 2014Assignee: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Harald Gossner
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Publication number: 20140145265Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.Type: ApplicationFiled: January 30, 2014Publication date: May 29, 2014Inventors: Mayank Shrivastava, Maryam Shojaei Baghini, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
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Publication number: 20140113423Abstract: In various embodiments, a method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device may include forming a first source/drain region, forming a second source/drain region, forming an active region electrically coupled between the first source/drain region and the second source/drain region, forming a trench disposed between the second source/drain region and at least a portion of the active region, forming a first isolation layer disposed over the bottom and the sidewalls of the trench, forming electrically conductive material disposed over the isolation layer in the trench, forming a second isolation layer disposed over the active region, and forming a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.Type: ApplicationFiled: December 24, 2013Publication date: April 24, 2014Applicant: Infineon Technologies AGInventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
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Patent number: 8701063Abstract: The number of scenarios analyzed for an electronic circuit is reduced to improve the processing time and resource requirements of electronic design automation processes. Each scenario is associated with a mode and a corner for the electronic circuit. Groups of scenarios corresponding to different corners for the same mode are identified. A winner scenario from each group is identified, for example, by selecting the dominant scenario from the group that covers the most number of violations in the group. The winner scenario is adjusted to account for violations of other scenarios of the group. The adjustment corresponding to a violation for a timing node from another scenario is performed by reducing the required time of the timing node in the winner scenario by a margin. The margin is determined based on timing information from the other scenario scaled to account for differences between the two scenarios.Type: GrantFiled: October 22, 2012Date of Patent: April 15, 2014Assignee: Synopsys, Inc.Inventors: Mayank Shrivastava, Chaeryung Park
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Publication number: 20140097465Abstract: Some aspects relate to a semiconductor device disposed on a semiconductor substrate. The device includes an STI region that laterally surrounds a base portion of a semiconductor fin. An anode region, which has a first conductivity type, and a cathode region, which has a second conductivity type, are arranged in an upper portion of the semiconductor fin. A first doped base region, which has the second conductivity type, is arranged in the base of the fin underneath the anode region. A second doped base region, which has the first conductivity type, is arranged in the base of the fin underneath the cathode region. A current control unit is arranged between the anode region and the cathode region. The current control unit is arranged to selectively enable and disable current flow in the upper portion of the fin based on a trigger signal. Other devices and methods are also disclosed.Type: ApplicationFiled: October 8, 2012Publication date: April 10, 2014Inventors: Mayank Shrivastava, Harald Gossner
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Patent number: 8681461Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device to protect a circuit from an ESD event. The ESD protection device includes first and second trigger elements. Upon detecting an ESD pulse, the first trigger element provides a first trigger signal having a first pulse length. The second trigger element, upon detecting the ESD pulse, provides a second trigger signal having a second pulse length. The second pulse length is different from the first pulse length. A primary shunt shunts power of the ESD pulse away from the ESD susceptible circuit based on the first trigger signal. A current control element selectively pumps current due to the ESD pulse into a substrate of the primary shunt based on the second trigger signal.Type: GrantFiled: March 26, 2012Date of Patent: March 25, 2014Assignee: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Christian Russ, Harald Gossner
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Patent number: 8664720Abstract: In one embodiment, the semiconductor device includes a first source of a first doping type disposed in a substrate. A first drain of the first doping type is disposed in the substrate. A first gate region is disposed between the first source and the first drain. A first channel region of a second doping type is disposed under the first gate region. The second doping type is opposite to the first doping type. A first extension region of the first doping type is disposed between the first gate and the first drain. The first extension region is part of a first fin disposed in or over the substrate. A first isolation region is disposed between the first extension region and the first drain. A first well region of the first doping type is disposed under the first isolation region. The first well region electrically couples the first extension region with the first drain.Type: GrantFiled: August 25, 2010Date of Patent: March 4, 2014Assignee: Infineon Technologies AGInventors: Mayank Shrivastava, Maryam Shojaei Baghini, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
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Patent number: 8654491Abstract: Some embodiments relate to an electrostatic discharge (ESD) protection device. The ESD protection device includes a first electrical path extending between the first and second circuit nodes and including a trigger element. A second electrical path extends between the first and second circuit nodes. The second electrical path includes a shunt element. A switching element is configured to trigger current flow through the shunt element based on both a state of the trigger element and a state of the switching element.Type: GrantFiled: April 2, 2012Date of Patent: February 18, 2014Assignee: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Christian Russ, Harald Gossner
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Patent number: 8643090Abstract: In various embodiments, a semiconductor device is provided. The semiconductor device may include a first source/drain region, a second source/drain region, an active region electrically coupled between the first source/drain region and the second source/drain region, a trench disposed between the second source/drain region and at least a portion of the active region, a first isolation layer disposed over the bottom and the sidewalls of the trench, electrically conductive material disposed over the isolation layer in the trench, a second isolation layer disposed over the active region, and a gate region disposed over the second isolation layer. The electrically conductive material may be coupled to an electrical contact.Type: GrantFiled: March 23, 2009Date of Patent: February 4, 2014Assignee: Infineon Technologies AGInventors: Mayank Shrivastava, Harald Gossner, Ramgopal Rao, Maryam Shojaei Baghini
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Publication number: 20140015010Abstract: In an embodiment of the invention, a semiconductor device includes a first region having a first doping type, a channel region having the first doping type disposed in the first region, and a retrograde well having a second doping type. The second doping type is opposite to the first doping type. The retrograde well has a shallower layer with a first peak doping and a deeper layer with a second peak doping higher than the first peak doping. The device further includes a drain region having the second doping type over the retrograde well. An extended drain region is disposed in the retrograde well, and couples the channel region with the drain region. An isolation region is disposed between a gate overlap region of the extended drain region and the drain region. A length of the drain region is greater than a depth of the isolation region.Type: ApplicationFiled: September 16, 2013Publication date: January 16, 2014Inventors: Mayank Shrivastava, Cornelius Christian Russ, Harald Gossner, Ramgopal Rao
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Patent number: 8629420Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.Type: GrantFiled: July 3, 2012Date of Patent: January 14, 2014Assignee: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Harald Gossner
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Publication number: 20140008733Abstract: Some aspects relate to a FinFET that includes a semiconductor fin disposed over a semiconductor substrate and extending laterally between a source region and a drain region. A shallow trench isolation (STI) region laterally surrounds a lower portion of the semiconductor fin, and an upper portion of the semiconductor fin remains above the STI region. A gate electrode traverses over the semiconductor fin to define a channel region in the semiconductor fin under the conductive gate electrode. A punch-through blocking region can extend between the source region and the channel region in the lower portion of the semiconductor fin. A drain extension region can extend between the drain region and the channel region in the lower portion of the semiconductor fin. Other devices and methods are also disclosed.Type: ApplicationFiled: July 3, 2012Publication date: January 9, 2014Applicant: Intel Mobile Communications GmbHInventors: Mayank Shrivastava, Harald Gossner