Abstract: A video decoding apparatus includes a bitstream parser, a calculator and a memory. The bitstream parser is provided to receive a video bitstream and extracting a set of constraints associated with the video bitstream, wherein the set of constraints has information associated with a direct_8×8_inference flag for a macroblock of a picture, wherein the macroblock has N sub-macroblock partitions. The calculator is provided to calculate first motion vector information associated with the macroblock and obtain second motion vector information associated with K of the N sub-macroblock partitions from the first motion vector information according to the information associated with the direct_8×8_inference flag, wherein K is less than N. The memory is provided to store the second motion vector information.

Abstract: A data buffering apparatus includes a plurality of storage devices and a storage controller. Each of the storage devices is arranged for only storing a partial data of one of a plurality of input images merged in a merged image when data of the merged image is received at a data input port of the data buffering apparatus. The storage controller is coupled to the storage devices, and arranged for alternately controlling stored partial data of the input images to be transmitted to an image/video processing device when the data of the merged image is received at the data input port.

Abstract: The invention provides a printed circuit board for mobile platforms. An exemplary embodiment of the printed circuit board for mobile platforms includes a core substrate having a first side. A ground plane covers the first side. A first insulating layer covers the ground plane. A plurality of first signal traces and a plurality of first ground traces are alternatively arranged on the first insulating layer. A second insulating layer connects to the first insulating layer. A plurality of second signal traces separated from each other is disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto.

Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator includes a multi-stage loop filter, a quantizer, and a digital-to-analog converter. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. Each stage of the multi-stage loop filter includes a feedback network. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. The digital-to-analog converter receives the digital output signal and converts the digital output signal to a compensation signal. The digital-to-analog converter provides the compensation signal to a plurality of internal nodes in the feedback network of the last stage of the multi-stage loop filter.

Abstract: A filter is provided. The filter receives an input signal and generates an output signal according to the input signal. The filter includes an input network, a high-pass network, and an operational circuit. The first input network provides a first normal path for the input signal to generate a first normal signal. The first high-pass network provides a first high-pass path for the input signal to generate a first high-pass signal. The operational circuit has first and second input terminals. The polarity of the second input terminal is inverse to that of the first input terminal. The operational circuit receives the first normal signal by the first input terminal and the first high-pass signal by the second input terminal such that a subtraction operation is performed on the first normal signal and the first high-pass filter to accomplish a low-pass filtering operation for generating the output signal.

Abstract: An electrostatic discharge (ESD) protection circuit is provided. A first NMOS transistor is coupled to a power line. A second NMOS transistor is coupled between the first transistor and a ground. A detection unit provides a detection signal when an ESD event occurs at the power line. A trigger unit turns on the second NMOS transistor and the first NMOS transistor in sequence in response to the detection signal, such that a discharge path is formed from the power line to the ground via the first and second NMOS transistors.

Abstract: A method of triggering and reporting traffic statistics in a cellular network is proposed. A UE establishes an RRC connection with a base station. The UE collects traffic statistics upon detecting a trigger event. The traffic statistics comprises packet inter-arrival time. The trigger event may be detected by the UE or by the base station. The UE then determines a representation of the traffic statistics and report the result to the base station. The report may be triggered by the UE or by the base station based on another trigger event. Upon receiving the traffic statistics, the base station determines RRC reconfiguration parameters. In one example, DRX timer values are determined based on intra-burst packet inter-arrival time. In another example, RRC release timer is determined based on inter-burst packet inter-arrival time.

Abstract: The invention provides an electronic apparatus. The electronic apparatus includes a Dynamic Random Access Memory (DRAM) and a DRAM controller. The DRAM receives at least one control and address signal and a clock signal, delays the clock signal by a predetermined value to obtain a delayed clock signal, samples the control and address signal according to the clock signal to obtain a first sample signal, samples the control and address signal according to the delayed clock signal to obtain a second sample signal, and compares the first sample signal with the second sample signal to obtain a status signal. The DRAM controller sends the control and address signal and the clock signal to the DRAM, receives the status signal from the DRAM, and adjusts a phase difference between the clock signal and the control and address signal according to the status signal.

Abstract: A method of collecting and providing traffic statistics in a cellular network in accordance is proposed. A UE establishes an RRC connection with a base station. The UE starts to collect traffic statistics that comprises a CDF curve or a PDF diagram for packet inter-arrival time. The UE may receive a measurement configuration from the base station for the traffic statistics collection. The UE then reports a representation of the traffic statistics to the base station for RRC reconfiguration. The UE may also receive a reporting request from the base station that specifies a representation format. The representation format includes one or more probability values at corresponding inter-arrival time points, at least one slope of the CDF, one or more steep events in the CDF, or a PDF range.

Abstract: A communication device with a power detection scheme is disclosed. The communication device includes a transmitter for transmitting an RF signal, a demodulator for demodulating the RF signal by utilizing a phase-modulated (PM) signal provided from the transmitter to generate a demodulated signal, a loopback circuit coupled between the transmitter and the demodulator for transmitting the RF signal and the PM signal from the transmitter to the demodulator when the power detection scheme is enabled, and a power detector for detecting power of the demodulated signal.

Abstract: A method of providing location option control for Minimization of Drive Test (MDT) in LTE systems is provided. In one embodiment, a UE or an eNB receives an MDT location request that comprises an MDT location option configuration having one or more location options. The UE or eNB determines a first location option based on the MDT location option configuration and initiates positioning for MDT measurements, reporting, and logging according to the first location option. In one novel aspect, each location option is associated with a priority. In addition to MDT measurements, reporting, and logging, a UE determines the best positioning procedure from a list of available location options. In one novel aspect, under a specific positioning objective, the UE prioritizes the list of available location options based on the signal strength and/or quality of cellular and WLAN signals.

Abstract: An enhanced connection recovery upon lost RRC connection due to radio link failure (RLF) or handover failure (HOF) is proposed. A UE first establishes an RRC connection in a source cell in a mobile communication network. Later on, the UE detects a failure event and starts an RRC reestablishment procedure in a target cell to restore the RRC connection. In a first novel aspect, a fast RLF process is applied to reduce the outage time in the serving cell. In a second novel aspect, an enhanced cell selection mechanism based on cell prioritization information is applied to reduce the outage time in the target cell. In one embodiment, multi-RAT registration is used to steer cell selection.

Abstract: An enhanced connection recovery upon lost RRC connection due to radio link failure (RLF) or handover failure (HOF) is proposed. A UE first establishes an RRC connection in a source cell in a mobile communication network. Later on, the UE detects a failure event and starts an RRC reestablishment procedure in a target cell to restore the RRC connection. In a first novel aspect, a fast NAS recovery process is applied to reduce the outage time in the target cell. In a second novel aspect, context fetching is used to reduce the outage time in the target cell. In a third novel aspect, a loss-less reestablishment procedure is proposed to reduce data loss during the connection recovery.

Abstract: An access method for a DRAM is provided. A row address is partitioned into a first portion and a second portion. The first portion of the row address via an address bus and a first active command via a command bus are provided to the DRAM. The second portion of the row address via the address bus and a second active command via the command bus are provided to the DRAM after the first active command is provided. A column address via the address bus and an access command via the command bus are provided to the DRAM after the second active command is provided. The address bus is formed by a plurality of address lines, and a quantity of the address lines is smaller than the number of bits of the row address, and the access command is a read command or a write command.

Abstract: A video processing method includes decoding a bitstream that includes a plurality of groups of pictures and each group of pictures comprises a frame sequence, determining whether a current frame of a current group of pictures to be displayed has macroblocks with forward reference to a previous frame of a previous group of pictures, wherein the current group of pictures is subsequent to the previous group of pictures, and displaying the current frame of the current group of pictures when the current frame has no macroblock with forward reference to the previous frame of the previous group of pictures. The previous frame of the previous group of pictures is determined to be referenced by the current frame of the current group of pictures according to information specified from the encoding of the current frame.

Abstract: A phase/frequency detector for control signal to controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.

Abstract: A flip chip package includes a substrate having a die attach surface; and a die mounted on the die attach surface with an active surface of the die facing the substrate, wherein the die is interconnected to the substrate via a plurality of copper pillar bumps on the active surface, wherein at least one of the plurality of copper pillar bumps has a bump width that is substantially equal to or smaller than a line width of a trace on the die attach surface of the substrate.

Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.

Abstract: A method for performing chip level electromagnetic interference (EMI) reduction is provided, where the method is applied to an electronic device. The method includes: providing at least one EMI suppression circuit within at least one chip of the electronic device; and utilizing the at least one EMI suppression circuit within the at least one chip to perform EMI reduction on at least one signal within the at least one chip. In particular, the at least one chip includes a first chip and a second chip; and the at least one EMI suppression circuit includes a first EMI suppression circuit positioned within the first chip, and further includes a second EMI suppression circuit positioned within the second chip. An associated apparatus is also provided.

Abstract: A driving circuit is provided. The driving circuit is capable of driving a load coupled to an output node of the driving circuit. The driving circuit includes an output-stage element, a first N-type metal-oxide-semiconductor (NMOS) transistor, and a first P-type metal-oxide-semiconductor (PMOS) transistor. The output-stage element is coupled between an operation voltage source and the output node. The first NMOS transistor has a gate, a drain coupled to the output node, and a source coupled to a ground. The first PMOS transistor has a gate, a drain coupled to the ground, and a source coupled to the output node. When the first NMOS transistor begins to be turned off, the first PMOS transistor is turned on, and a voltage at the drain of the first NMOS transistor is clamped to be lower than a breakdown trigger voltage of the first NMOS transistor.