Abstract: A method of forming an integrated circuit with a semiconductor substrate is provided. A gate dielectric is formed on the semiconductor substrate, and a gate is formed on the gate dielectric. Source/drain junctions are formed in the semiconductor substrate. A silicide is formed on the source/drain junctions and on the gate. An interlayer dielectric having contact holes therein is formed above the semiconductor substrate. Contact liners are formed in the contact holes, and contacts are then formed over the contact liners. The contact liners are nitrides of the contact material, and formed at a temperature below the thermal budget for the silicide.

Abstract: An system IC is partitioned into test ICs that have a sub-set of the functionality of the system IC. The test ICs have chip I/O pads conforming to a sub-set arrangement of the system IC chip I/O pads. A packaging module is designed to accept means for attaching and fanning-out the system IC chip I/O pads to lower density packaging I/O pads. A test IC is electrically coupled to the packaging module and tested by programming signals and power to the signal and power pads on the module packaging I/O pads corresponding to chip I/O pads for the test IC. Functionality of the system IC may be partitioned into a plurality of test ICs, each with chip I/O pads that conform to an individual sub-set of the system IC I/Os. Two or more of the plurality of test ICs are coupled to the system IC packaging module for testing.

Abstract: Aspects for locating chip-level defects through emission imaging of a semiconductor device are described. The aspects include providing a semiconductor device for inspection within an emission imaging system. Emission detection from a frontside and backside of the semiconductor device substantially simultaneously is then performed in the emission imaging system, wherein the emissions detected indicate potential defects within the semiconductor device.

Abstract: The present inventive principles provide a method and system for performing backside voltage contrast on an SOI device. The SOI semiconductor device includes a bulk silicon, a box insulator residing on the bulk silicon and a silicon region on the box insulator. The SOI semiconductor device further includes a plurality of structures in the silicon region, the plurality of structures includes a conductive structure. The method and system include mechanical dimpling and chemical etching of the substrate to expose the box insulator. Optionally, a second chemical etch to remove at least a portion of the box insulator may be performed. A charged particle beam, such as energetic electrons from an SEM, for example, may be directed at the backside of the device, and emitted secondary electrons observed.

Abstract: A method and system for verifying an architecture of a semiconductor device is disclosed. The method and system include providing a tester, a detector and an image processing unit. The tester applies at least one voltage to at least one selected portion of the semiconductor device. The at least one voltage is sufficient for the at least one selected portion of the semiconductor device to produce a particular level of radiation. The detector detects the radiation. The image processing unit is coupled with the detector and the tester. The image processing unit captures an image from the detector. The image indicates at least one physical location of the at least one selected portion of the semiconductor device. The architecture of the memory device can be verified by comparing the at least one selected portion of the semiconductor device to the at least one physical location.

Abstract: An system IC is partitioned into test ICs that have a sub-set of the functionality of the system IC. The test ICs have chip I/O pads conforming to a sub-set arrangement of the system IC chip I/O pads. A packaging module is designed to accept means for attaching and fanning-out the system IC chip I/O pads to lower density packaging I/O pads. A test IC is electrically coupled to the packaging module and tested by programming signals and power to the signal and power pads on the module packaging I/O pads corresponding to chip I/O pads for the test IC. Functionality of the system IC may be partitioned into a plurality of test ICs, each with chip I/O pads that conform to an individual sub-set of the system IC I/Os. Two or more of the plurality of test ICs are coupled to the system IC packaging module for testing.

Abstract: A method and semiconductor device for detecting a heat generating failure in an unpassivated semiconductor device. The semiconductor device has an unpassivated surface and a heat generating failure, e.g., short circuit. A coating may be applied to the unpassivated surface of the semiconductor device. The coating may be non-electrically conducting and capable of localizing heat generated by the failure in a particular area. The semiconductor device may be biased. The failure may then be detected by detecting a location of the heat generated by the failure in the coating.

Abstract: A method of forming an integrated circuit and a structure therefore is provided. A gate dielectric is formed on a semiconductor substrate, and a gate is formed over the gate dielectric. Shallow source/drain junctions are formed in the semiconductor substrate. A sidewall spacer is formed around the gate. Deep source/drain junctions are formed in the semiconductor substrate using the sidewall spacer. A siliciding spacer is formed over the sidewall spacer after forming the shallow and deep source/drain junctions. A silicide is formed on the deep source/drain junctions adjacent the siliciding spacer, and a dielectric layer is deposited above the semiconductor substrate. Contacts are then formed in the dielectric layer to the silicide.

Abstract: A method and apparatus for identifying individual semiconductor die that originate from a semiconductor substrate containing a plurality of die is disclosed. Aspects of the invention include physically associating a respective die ID with at least a portion of individual die on the wafer, and storing the die ID and wafer fabrication information in a database. During subsequent testing of the die, the die ID is used to retrieve the wafer fabrication information from the database, thereby aiding a determination as to a cause of a failure of the die.

Abstract: A method and system for performing failure analysis on a silicon on insulator (SOI) semiconductor device is disclosed. The SOI device includes a plurality of conductive structures in a silicon region. The silicon resides on a box insulator, which resides on a silicon substrate. The method and system include providing a cross-section of the SOI semiconductor device. The cross-section of the SOI semiconductor device includes a portion of the plurality of conductive structures. The method and system also include staining the cross-section of the SOI semiconductor device using a stain. The stain etches the silicon region in the SOI semiconductor device without etching a remaining portion of the SOI semiconductor device not composed of silicon.

Abstract: Aspects for revealing active regions of a silicon-on-insulator (SOI) circuit for inspection from a backside of a DUT are described. The aspects include etching a substrate layer of an SOI circuit and removing a buried oxide layer beneath the substrate layer. From these steps, active regions beneath the buried oxide layer are revealed.

Abstract: A method and system for deprocessing a semiconductor device is disclosed. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system include anisotropically plasma etching the intermetal dielectric layer at an oblique angle and rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer. In another aspect the method and system include a semiconductor device deprocessed using the method in accordance with the present invention. In another aspect, the present invention includes a system for deprocessing the semiconductor device.

Abstract: A method and apparatus for holding and delayering a die include an outer member (10) that receives an inner member (20), and a set screw (25) and set screw hole (12) for securing the position of the inner member (20) within the outer member (10). A die (50) is attached to the inner member (20), and the apparatus is then used to apply the die (50) to an abrasive disk (200) which is attached to a rotatable wheel (300) and is delayered by progressive abrading. The outer member (10) provides stability and precision to the delayering operation. The inner member (20) provides portability and control to the delayering operation.

Abstract: A method and system for deprocessing a semiconductor device is disclosed. The semiconductor device has a plurality of structures and an intermetal dielectric layer. The method and system include anisotropically plasma etching the intermetal dielectric layer at an oblique angle and rotating the semiconductor device during the plasma etch to reduce or eliminate build up of a material on the plurality of structures due to the plasma etch of the intermetal dielectric layer. In another aspect the method and system include a semiconductor device deprocessed using the method in accordance with the present invention. In another aspect, the present invention includes a system for deprocessing the semiconductor device.

Abstract: A protection circuit structure for use with silicon-on-insulator integrated circuits is provided so as to improve electrostatic discharge protection capability. The protection circuit structure includes a P/N junction defining a protection diode. The protection diode is formed underneath an electrically conductive input pad associated with a conventional SOI semiconductor device.

Abstract: A method and system for decapsulating a multi-chip package is disclosed. The multi-chip package includes a first die and a second die. The first die resides above the second die. The method and system include mechanically removing at least a portion of the first die substantially without destroying the portion of a second die. The method and system also include removing a portion of the multi-chip package between the first die and the second die to expose a portion of the second die substantially without destroying the portion of a second die.

Abstract: A fixture assembly of a unique construction is provided for use with a decapsulating machine so as to prevent damage to a FBGA package during decapsulation. The fixture assembly includes a retaining gasket for holding and aligning the FBGA package in the decapsulating machine, a spacer element for protecting the solder balls of the FBGA package, and a cover for receiving the pressure from a spring-loaded arm of the decapsulating machine. As a result, the FBGA package is prevented from being over etched by the sulfuric acid during decapsulation. In addition, damage to the solder balls are prevented due to excess pressure from the spring-loaded arm.

Abstract: Aspects for a decapsulation system and technique are described. In a method aspect, a portable decapsulation system is provided beneath at least one integrated circuit device on a printed circuit board. Package decapsulation of the least one integrated circuit device occurs through acid blasting by the portable decapsulation system. The portable decapsulation system includes a beaker, fuming acid within the beaker, and a sealed fitting for the beaker and holding an electronic device being decapsulated. Capillaries within the sealed fitting through which the fuming acid is released acid blast the electronic device, and a waste tube coupled to the sealed fitting for removal of solid waste during the acid blast.

Abstract: A system and method for identifying a location of a short in a circuit of a semiconductor device is disclosed. The method and system includes providing a power supply and providing a power distribution network coupled to the power supply. The power distribution network is for distributing power to a portion of the circuit. The power distribution network further including means for selectively disconnecting a portion of the power distribution network. The portion of the power distribution network supplies power to the location of the short.

Abstract: A method and system for removing a die from a semiconductor package is disclosed. The semiconductor package includes the die and a ceramic base. The die has a first face, a second face and a plurality of sides. The second face of the die is coupled with the ceramic base. The method and system include covering at least the first face and a portion of the plurality of sides of the die with a hard wax and encapsulating the hard wax and at least a first portion of the ceramic base in a resin. The method and system also include removing at least a second portion of the ceramic base to expose the second face of the die and removing the hard wax to free the die.