Patents by Inventor Mehul Shah

Mehul Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12155788
    Abstract: The disclosed system provides a facility for split billing for a single user on multiple billing systems. The disclosed system activates the user on each respective billing system using a unique pairing, such as an international mobile subscriber identity that identifies the user, and a mobile station international subscriber directory number that identifies a particular user device. As device data is routed through a telecommunication network via each access point name (APN), the network generates call detail records (CDRs), which include an indication of the APN used. The CDRs are routed to a mediation platform that uses the received APN information to route each CDR to the appropriate target billing system and to the appropriate service types.
    Type: Grant
    Filed: March 29, 2022
    Date of Patent: November 26, 2024
    Assignee: T-Mobile USA, Inc.
    Inventor: Mehul Shah
  • Publication number: 20240330228
    Abstract: Apparatuses, methods, systems, and program products are disclosed for dynamic baseboard management controller memory use. A method includes determining, by use of a processor, presence of main memory of a computing device, in response to determining that the main memory is not present in the computing device, preparing at least a portion of a memory device of a baseboard management controller for use by the processor, and making the at least a portion of the memory device of the BMC available to the processor.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Glenn D. Johnson, Ajay Dholakia, Ming Lei
  • Publication number: 20240330070
    Abstract: A method for automatically switching between partition configurations at a scheduled time period includes storing, at a service processor, a plurality of partition configurations for a computing system, the plurality of partition configurations allocating hardware resources of the computing system. The method includes associating a configuration schedule with the plurality of partition configurations, where each of the plurality of partition configurations is associated with a scheduled time period, and booting the computing system to a particular partition configuration at a particular scheduled time period corresponding to the particular partition configuration.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Gary D. Cudak, Pravin S. Patel, Mehul Shah, James Parsonese
  • Publication number: 20240331657
    Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on system events includes monitoring a system state for each of two or more systems sharing an electronic display, where each of the two or more systems includes a processor executing an instance of an operating system, selecting a system of the two or more systems sharing the electronic display in response to determining that a change has occurred in the system state of the of the selected system, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to the electronic display.
    Type: Application
    Filed: March 31, 2023
    Publication date: October 3, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Patent number: 12099391
    Abstract: A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: September 24, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Patent number: 12080436
    Abstract: Thorium-based fuel bundles according to one or more embodiments of the present invention provide a fresh fuel bundle comprising a first ring of fuel pins and a second ring of fuel pins. Each ring fuel pin has a fuel composition comprising uranium and thorium. The first ring fuel pins differ from the second ring fuel pins in each of the thorium wt %, uranium wt %, and 235U enrichment.
    Type: Grant
    Filed: June 15, 2023
    Date of Patent: September 3, 2024
    Assignee: CLEAN CORE THORIUM ENERGY LLC
    Inventors: Mehul Shah, Rida Milany, Koroush Shirvan
  • Patent number: 12067404
    Abstract: A baseboard management controller in a multi-processor system may perform operations including: identifying a partitioning mode (partitioned state or unified state) to implement on the multi-processor system having first and second central processing units (CPUs) located on a single motherboard; accessing, in response to the partitioned state, a first partitioned node configuration (P1C) for a first partitioned node (P1) and a second partitioned node configuration (P2C) for a second partitioned node (P2), wherein P1C identifies a first firmware interface level (F1L) and a first operating system to be used by P1, and wherein P2C identifies a second firmware interface level (F2L) and a second operating system to be used by P2; and causing the first CPU to load a first firmware interface having the identified F1L identified in the P1C and causing the second CPU to load a second firmware interface having the F2L identified in the P2C.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: August 20, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Patent number: 12059938
    Abstract: A vehicle comprising a first leaf spring connected to a chassis so as to, while deflecting, allow relative vertical movement between the chassis and a wheel axle and thereby also between the chassis and wheels, and a control circuitry configured to: compare the signal indicative of the actual path followed by the wind-up center with a representation of a reference path that the wind-up center of the first leaf spring should follow when the first leaf spring is well-functioning and deflects as intended; determine whether a difference between the actual path and the reference path is greater than a threshold value; and, in response to the determined difference greater than the threshold, generate an alarm signal indicative of a detected or possibly detected leaf spring failure.
    Type: Grant
    Filed: October 26, 2023
    Date of Patent: August 13, 2024
    Assignee: Volvo Truck Corporation
    Inventors: Dinkar Nalawade, Mehul Shah, Anish Sivankutty
  • Publication number: 20240266079
    Abstract: Thorium-based fuel bundles according to one or more embodiments of the present invention provide a fresh fuel bundle comprising a first ring of fuel pins and a second ring of fuel pins. Each ring fuel pin has a fuel composition comprising uranium and thorium. The first ring fuel pins differ from the second ring fuel pins in each of the thorium wt %, uranium wt %, and 235U enrichment.
    Type: Application
    Filed: June 15, 2023
    Publication date: August 8, 2024
    Inventors: Mehul SHAH, Rida MILANY, Koroush SHIRVAN
  • Patent number: 12050920
    Abstract: A baseboard management controller in a multi-processor system may perform operations including: causing, during a first time period, the system to operate in a partitioned state with a first partitioned node including a first subset of components of the system and a second partitioned node including a second subset of components of the system, wherein the first and second partitioned nodes are independently operable nodes having their own operating systems, and wherein the first partitioned node boots from a first boot drive that is included in the first subset; causing, during a second time period, the system to operate in a unified state with a single unified node including components from both the first and second subsets of components, wherein the single unified node has its own operating system; and causing the first boot drive to be inaccessible to the second partitioned node and the single unified node.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: July 30, 2024
    Inventors: Gary D. Cudak, Pravin S. Patel, Mehul Shah, James Parsonese
  • Patent number: 12047002
    Abstract: Methods and systems for operating a multiphase voltage regulator are described. The multiphase voltage regulator can include a plurality of power stages. A controller can be connected to the plurality of power stages. The controller can detect a number of activated power stages among the plurality of power stages. The controller can adjust a gain of a current sense feedback loop of the controller to control a load-transient response of the multiphase voltage regulator. The adjustment to the gain can be based on the number of activated power stages.
    Type: Grant
    Filed: December 31, 2021
    Date of Patent: July 23, 2024
    Assignee: Renesas Electronics America Inc.
    Inventors: Michael Jason Houston, Mehul Shah, Warren Schroeder, Akshat Shenoy
  • Publication number: 20240211275
    Abstract: A baseboard management controller in a multi-processor system may perform operations including: identifying a partitioning mode (partitioned state or unified state) to implement on the multi-processor system having first and second central processing units (CPUs) located on a single motherboard; accessing, in response to the partitioned state, a first partitioned node configuration (P1C) for a first partitioned node (P1) and a second partitioned node configuration (P2C) for a second partitioned node (P2), wherein P1C identifies a first firmware interface level (F1L) and a first operating system to be used by P1, and wherein P2C identifies a second firmware interface level (F2L) and a second operating system to be used by P2; and causing the first CPU to load a first firmware interface having the identified F1L identified in the P1C and causing the second CPU to load a second firmware interface having the F2L identified in the P2C.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Publication number: 20240211372
    Abstract: A baseboard management controller in a partitionable multi-processor system may perform operations including receiving a plurality of event notifications from the partitionable multi-processor system including one or more event notifications from a first partitioned node including a first subset of hardware devices of the multi-processor system and one or more event notifications from a second partitioned node including a second subset of the hardware devices of the multi-processor system, wherein each event notification identifies an event and a specific one of the hardware devices that experienced the event. The operations may further include receiving a request for an event log for the first partitioned node and providing the requested event log for the first partitioned node including only those event notifications that identify a hardware device that is included in the first partitioned node.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Publication number: 20240211274
    Abstract: A baseboard management controller in a multi-processor system may perform operations including: causing, during a first time period, the system to operate in a partitioned state with a first partitioned node including a first subset of components of the system and a second partitioned node including a second subset of components of the system, wherein the first and second partitioned nodes are independently operable nodes having their own operating systems, and wherein the first partitioned node boots from a first boot drive that is included in the first subset; causing, during a second time period, the system to operate in a unified state with a single unified node including components from both the first and second subsets of components, wherein the single unified node has its own operating system; and causing the first boot drive to be inaccessible to the second partitioned node and the single unified node.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Pravin S. Patel, Mehul Shah, James Parsonese
  • Publication number: 20240211423
    Abstract: A method for automatically switching input/output (“I/O”) between partitioned systems based on power usage includes monitoring power usage for each of two or more systems, selecting a system of the two or more systems in response to power usage of the of the system reaching a power usage threshold, and switching an input of an I/O switch to send data for display of one or more elements of the selected system to an electronic display.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Publication number: 20240211427
    Abstract: A multi-processor system includes first and second central processing units (CPUs) connected by a processor interconnect, a single baseboard management controller for managing operation of the first and second CPUs, wherein the first and second CPUs are operable as a single unified node, and a single keyboard, video and mouse connection, wherein the single keyboard, video and mouse connection includes a video controller and a USB controller. The multi-processor system may further comprise a multiplexer connected to the video controller and the USB controller, wherein the multiplexer has a selectable PCIe connection to either the first central processing unit or the second central processing unit. Program instructions may be executable by the baseboard management controller to send a selection signal to the multiplexer.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Publication number: 20240211316
    Abstract: Embodiments provide a method and a computer program product providing program instructions executable by a processor of a baseboard management controller in a multi-processor system to cause the processor to perform various operations. The operations include identifying a number of cores present in each of a plurality of central processing units in the multi-processor system, initiating operation of the multi-processor system as a single unified node in response to each of the plurality of central processing units having an equal number of cores, and initiating partitioning of the multi-processor system into first and second independent partitioned nodes in response to a first set of one or more of the central processing units each having a first number of cores and a second set of one or more of the central processing units each having a second number of cores that is different than the first number of cores.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Pravin S. Patel, Mehul Shah, James Parsonese
  • Publication number: 20240211008
    Abstract: A partitionable multi-processor system includes a first plurality of components of the multi-processor system forming a first partitioned node that is operable as a first independent node, a second plurality of components of the multi-processor system forming a second partitioned node that is operable as a second independent node and a system controller that is configured to selectively and independently control separate power, clock, and/or reset signals to the first plurality of components forming the first partitioned node and the second plurality of components forming the second partitioned node in response to receiving a first partitioning mode instruction from a baseboard management controller (BMC) that identifies a partitioned state and configured to selectively control the separate power, clock, and/or reset signals to the first and second pluralities of components in a unified manner in response to receiving a second partitioning mode instruction from the BMC that identifies a unified state.
    Type: Application
    Filed: December 22, 2022
    Publication date: June 27, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese
  • Patent number: 12020278
    Abstract: A vertically integrated retail system includes an embedded storefront adapted to operate in a distributed manner through independent units embedded in different web sites or content in other host applications. Each unit of the embedded storefront enables a user to purchase goods, services, or other entities without leaving the host application. The units are modules that may be inserted into a web page, application, game, or other electronic media. Units can include product content such as video or animation, images, text, audio, music, or any other type of interactive or non-interactive electronic content. A user may receive virtual currency, virtual goods (such as virtual items or enhancements within a game application), or other rewards for completing transactions using the unit in the host application. Units may be embedded in host content via hyperlinks included in the content or through an application programming interface of a host content provider.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: June 25, 2024
    Assignee: BYTEDANCE INC.
    Inventors: Rajiv Bhat, Vijay Chittoor, Ryoma Ito, Mehul Shah
  • Patent number: 11983053
    Abstract: A system includes a partitionable multi-processor motherboard that has multiple central processing units, wherein the multi-processor motherboard may be configured to operate as a single unified node or configured to operate as multiple independent partitioned nodes. The system further comprises a single power button that is accessible to a user, wherein the single power button generates an output signal while being pressed, and an integrated circuit installed on the motherboard and connected to receive the output signal from the power button, wherein the integrated circuit stores a first button press gesture definition associated with selection of a first partitioned node, a second button press gesture definition associated with selection of a second partitioned node, and a third button press gesture definition associated with sequencing power to the selected one of the first or second partitioned nodes.
    Type: Grant
    Filed: December 22, 2022
    Date of Patent: May 14, 2024
    Inventors: Gary D. Cudak, Mehul Shah, Pravin S. Patel, James Parsonese