Patents by Inventor Mei-Hui Fu
Mei-Hui Fu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11532503Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: GrantFiled: November 23, 2020Date of Patent: December 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Publication number: 20220375863Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: ApplicationFiled: July 26, 2022Publication date: November 24, 2022Inventors: Pin-Wen CHEN, Mei-Hui FU, Hong-Mao LEE, Wei-Jung LIN, Chih-Wei CHANG
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Patent number: 11482495Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: GrantFiled: November 13, 2019Date of Patent: October 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, ltd.Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-Jung Lin, Chih-Wei Chang
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Publication number: 20210193517Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: March 8, 2021Publication date: June 24, 2021Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu-Shih Wang, Ya-Yi Cheng, I-Li Chen
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Publication number: 20210074580Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: November 23, 2020Publication date: March 11, 2021Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10943823Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: GrantFiled: October 16, 2019Date of Patent: March 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
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Patent number: 10847411Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: GrantFiled: August 30, 2019Date of Patent: November 24, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10804140Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: GrantFiled: March 29, 2018Date of Patent: October 13, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10756017Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.Type: GrantFiled: March 21, 2019Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
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Publication number: 20200176382Abstract: A method for fabricating a semiconductor arrangement includes removing a portion of a first dielectric layer to form a first recess defined by sidewalls of the first dielectric layer, forming a first conductive layer in the first recess, removing a portion of the first conductive layer to form a second recess defined by the sidewalls of the first dielectric layer, forming a second conductive layer in the second recess, where the second conductive layer contacts the first conductive layer, forming a second dielectric layer over the second conductive layer, removing a portion of the second dielectric layer to form a third recess defined by sidewalls of the second dielectric layer, where the second conductive layer is exposed through the third recess, and forming a third conductive layer in the third recess, where the third conductive layer contacts the second conductive layer.Type: ApplicationFiled: November 13, 2019Publication date: June 4, 2020Inventors: Pin-Wen Chen, Mei-Hui Fu, Hong-Mao Lee, Wei-jung Lin, Chih-Wei Chang
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Publication number: 20200051858Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: October 16, 2019Publication date: February 13, 2020Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Shih Wang, Ya-Yi Cheng, I-Li Chen
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Publication number: 20190385904Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: August 30, 2019Publication date: December 19, 2019Inventors: Pin-Wen Chen, Chia-Han Lai, Mei-Hui Fu, Min-Hsiu Hung, Ya-Yi Cheng
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Patent number: 10475702Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: GrantFiled: March 14, 2018Date of Patent: November 12, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen Chen, Chia-Han Lai, Chih-Wei Chang, Mei-Hui Fu, Ming-Hsing Tsai, Wei-Jung Lin, Yu Shih Wang, Ya-Yi Cheng, I-Li Chen
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Publication number: 20190304833Abstract: Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.Type: ApplicationFiled: March 29, 2018Publication date: October 3, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen CHEN, Chia-Han LAI, Mei-Hui FU, Min-Hsiu HUNG, Ya-Yi CHENG
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Publication number: 20190287851Abstract: The present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In some embodiments, a structure includes a first dielectric layer over a substrate, a first conductive feature through the first dielectric layer, the first conductive feature comprising a first metal, a second dielectric layer over the first dielectric layer, and a second conductive feature through the second dielectric layer having a lower convex surface extending into the first conductive feature, wherein the lower convex surface of the second conductive feature has a tip end extending laterally under a bottom boundary of the second dielectric layer.Type: ApplicationFiled: March 14, 2018Publication date: September 19, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Pin-Wen CHEN, Chia-Han LAI, Chih-Wei CHANG, Mei-Hui FU, Ming-Hsing TSAI, Wei-Jung LIN, Yu Shih WANG, Ya-Yi CHENG, I-Li CHEN
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Publication number: 20190221522Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.Type: ApplicationFiled: March 21, 2019Publication date: July 18, 2019Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
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Patent number: 10269713Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.Type: GrantFiled: November 3, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
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Publication number: 20180076144Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.Type: ApplicationFiled: November 3, 2017Publication date: March 15, 2018Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
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Patent number: 9831183Abstract: Contact structures and methods of forming contacts structures are contemplated by this disclosure. A structure includes a dielectric layer over a substrate, an adhesion layer, a silicide, a barrier layer, and a conductive material. The dielectric layer has an opening to a surface of the substrate. The adhesion layer is along sidewalls of the opening. The silicide is on the surface of the substrate. The barrier layer is on the adhesion layer and the silicide, and the barrier layer directly adjoins the silicide. The conductive material is on the barrier layer in the opening.Type: GrantFiled: November 4, 2014Date of Patent: November 28, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Mei-Hui Fu, Sheng-Hsuan Lin
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Patent number: 9589892Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a contact layer over a substrate, a dielectric layer over the contact layer, a silicide layer over the exposed portion of the contact layer, a barrier layer along sidewalls of the opening, an alloy layer over the barrier layer, a glue layer over the alloy layer, and a conductive plug over the glue layer, wherein the dielectric layer has an opening, and the opening exposes a portion of the contact layer.Type: GrantFiled: May 20, 2016Date of Patent: March 7, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Hung Lin, Mei-Hui Fu, Wei-Jung Lin, You-Hua Chou, Chia-Lin Hsu, Hon-Lin Huang, Shih-Chi Lin