Patents by Inventor Meikei Ieong
Meikei Ieong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9355887Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: GrantFiled: January 12, 2012Date of Patent: May 31, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 9236445Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.Type: GrantFiled: January 16, 2014Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Ken-Ichi Goto, Zhiqiang Wu
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Publication number: 20150200272Abstract: The disclosure provides a method of forming a transistor. In this method, a dummy gate structure is formed over a semiconductor substrate. Source/drain regions are then formed in the semiconductor substrate such that a channel region, which is arranged under the dummy gate structure in the semiconductor substrate, separates the source/drains from one another. After the source/drain regions have been formed, the dummy gate structure is removed. After the dummy gate structure has been removed, a surface region of the channel region is removed to form a channel region recess. A replacement channel region is then epitaxially grown in the channel region recess.Type: ApplicationFiled: January 16, 2014Publication date: July 16, 2015Inventors: Chia-Wen Liu, Tsung-Hsing Yu, Wei-Hao Wu, Meikei Ieong, Ken-Ichi Goto, Zhiqiang Wu
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Patent number: 8785281Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: February 9, 2012Date of Patent: July 22, 2014Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
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Publication number: 20120142181Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: ApplicationFiled: February 9, 2012Publication date: June 7, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
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Publication number: 20120104511Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: ApplicationFiled: January 12, 2012Publication date: May 3, 2012Applicant: International Business Machines CorporationInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 8158481Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: GrantFiled: January 7, 2010Date of Patent: April 17, 2012Assignee: International Business Machines CorporationInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
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Patent number: 8097516Abstract: The present invention provides a semiconductor structure in which different types of devices are located upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. In the semiconductor structure of the present invention, a dual trench isolation scheme is employed whereby a first trench isolation region of a first depth isolates devices of different polarity from each other, while second trench isolation regions of a second depth, which is shallower than the first depth, are used to isolate devices of the same polarity from each other. The present invention further provides a dual trench semiconductor structure in which pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane. In accordance with the present invention, the devices of different polarity, i.e., nFETs and pFETs, are bulk-like devices.Type: GrantFiled: July 9, 2008Date of Patent: January 17, 2012Assignee: International Business Machines CorporationInventors: Victor Chan, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Chun-yung Sung, Min Yang
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Patent number: 8080838Abstract: A FINFET-containing structure having multiple FINs that are merged together without source/drain contact pads or a local interconnect is provided. The structure includes a plurality of semiconducting bodies (i.e., FINs) which extend above a surface of a substrate. A common patterned gate stack surrounds the plurality of semiconducting bodies and a nitride-containing spacer is located on sidewalls of the common patterned gate stack. An epitaxial semiconductor layer is used to merge each of the semiconducting bodies together.Type: GrantFiled: May 1, 2009Date of Patent: December 20, 2011Assignee: International Business Machines CorporationInventors: Leland Chang, Wilfried E. Haensch, Meikei Ieong, Ghavam Shahidi, Huiling Shang
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Patent number: 7960790Abstract: A double-gate transistor having front (upper) and back gates that are aligned laterally is provided. The double-gate transistor includes a back gate thermal oxide layer below a device layer; a back gate electrode below a back gate thermal oxide layer; a front gate thermal oxide above the device layer; a front gate electrode layer above the front gate thermal oxide and vertically aligned with the back gate electrode; and a transistor body disposed above the back gate thermal oxide layer, symmetric with the first gate. The back gate electrode has a layer of oxide formed below the transistor body and on either side of a central portion of the back gate electrode, thereby positioning the back gate self-aligned with the front gate. The transistor also includes source and drain electrodes on opposite sides of said transistor body.Type: GrantFiled: May 13, 2008Date of Patent: June 14, 2011Assignee: International Business Machines CorporationInventors: Omer H. Dokumaci, Bruce B. Doris, Kathryn W. Guarini, Suryanararyan G. Hegde, Meikei Ieong, Erin Catherine Jones
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Patent number: 7943486Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: GrantFiled: May 6, 2008Date of Patent: May 17, 2011Assignee: International Business Machines CorporationInventors: Victor Chan, Massimo V. Fischetti, John M. Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul M. Solomon, Chun-yung Sung, Min Yang
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Patent number: 7833854Abstract: The present invention provides a method of integrating semiconductor devices such that different types of devices are formed upon a specific crystal orientation of a hybrid substrate that enhances the performance of each type of device. Specifically, the present invention provides a method of integrating semiconductor devices such that pFETs are located on a (110) crystallographic plane, while nFETs are located on a (100) crystallographic plane of a planar hybrid substrate. The method of the present invention also improves the performance of creating SOI-like devices with a combination of a buried insulator and counter-doping layers. The present invention also relates to semiconductor structures that are formed utilizing the method of the present invention.Type: GrantFiled: June 24, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Meikei Ieong, Min Yang
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Patent number: 7834425Abstract: The present invention relates to a hybrid orientation semiconductor-on-insulator (SOI) substrate structure that contains a base semiconductor substrate with one or more first device regions and one or more second device regions located over the base semiconductor substrate. The one or more first device regions include an insulator layer with a first semiconductor device layer located atop. The one or more second device regions include a counter-doped semiconductor layer with a second semiconductor device layer located atop. The first and the second semiconductor device layers have different crystallographic orientations. Preferably, the first (or the second) device regions are n-FET device regions, and the first semiconductor device layer has a crystallographic orientation that enhances electron mobility, while the second (or the first) device regions are p-FET device regions, and the second semiconductor device layer has a different surface crystallographic orientation that enhances hole mobility.Type: GrantFiled: May 5, 2008Date of Patent: November 16, 2010Assignee: International Business Machines CorporationInventors: Meikei Ieong, Xinlin Wang, Min Yang
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Patent number: 7790538Abstract: A structure and method of fabrication for PFET devices in a compressively strained Ge layer is disclosed. The fabrication method of such devices is compatible with standard CMOS technology and it is fully scalable. The processing includes selective epitaxial depositions of an over 50% Ge content buffer layer, a pure Ge layer, and a SiGe top layer. Fabricated buried channel PMOS devices hosted in the compressively strained Ge layer show superior device characteristics relative to similar Si devices.Type: GrantFiled: May 10, 2008Date of Patent: September 7, 2010Assignee: International Business Machines CorporationInventors: Huiling Shang, Meikei Ieong, Jack Oon Chu, Kathryn W. Guarini
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Patent number: 7759772Abstract: A method of forming a hybrid SOI substrate comprising an upper Si-containing layer and a lower Si-containing layer, wherein the upper Si-containing layer and the lower Si-containing layer have different crystallographic orientations. In accordance with the present invention, the buried insulating region may be located within one of the Si-containing layers or through an interface located between the two Si-containing layers.Type: GrantFiled: October 18, 2006Date of Patent: July 20, 2010Assignee: International Business Machines CorporationInventors: Meikei Ieong, Devendra K. Sadana, Ghavam Shahidi
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Patent number: 7723207Abstract: A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to form a laminated 3D chip.Type: GrantFiled: April 19, 2007Date of Patent: May 25, 2010Assignee: International Business Machines CorporationInventors: Syed M. Alam, Ibrahim M. Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N. Kudva, David S. Kung, Mark A. Lavin, Arifur Rahman
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Patent number: 7713807Abstract: An integrated semiconductor structure containing at least one device formed upon a first crystallographic surface that is optimal for that device, while another device is formed upon a second different crystallographic surface that is optimal for the other device is provided. The method of forming the integrated structure includes providing a bonded substrate including at least a first semiconductor layer of a first crystallographic orientation and a second semiconductor layer of a second different crystallographic orientation. A portion of the bonded substrate is protected to define a first device area, while another portion of the bonded substrate is unprotected. The unprotected portion of the bonded substrate is then etched to expose a surface of the second semiconductor layer and a semiconductor material is regrown on the exposed surface. Following planarization, a first semiconductor device is formed in the first device region and a second semiconductor device is formed on the regrown material.Type: GrantFiled: December 18, 2007Date of Patent: May 11, 2010Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Kathryn W. Guarini, Meikei Ieong, Shreesh Narasimha, Kern Rim, Jeffrey W. Sleight, Min Yang
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Publication number: 20100112800Abstract: Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.Type: ApplicationFiled: January 7, 2010Publication date: May 6, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Tze-Chiang Chen, Meikei Ieong, Rajarao Jammy, Mukesh V. Khare, Chun-yung Sung, Richard Wise, Hongwen Yan, Ying Zhang
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Patent number: 7704839Abstract: A field effect transistor (FET) comprises a substrate; a buried oxide (BOX) layer over the substrate; a current channel region over the BOX layer; source/drain regions adjacent to the current channel region; a buried high-stress film in the BOX layer and regions of the substrate, wherein the high-stress film comprises any of a compressive film and a tensile film; an insulating layer covering the buried high-stress film; and a gate electrode over the current channel region, wherein the high-stress film is adapted to create mechanical stress in the current channel region, wherein the high-stress film is adapted to stretch the current channel region in order to create the mechanical stress in the current channel region; wherein the mechanical stress comprises any of compressive stress and tensile stress, and wherein the mechanical stress caused by the high-stress film causes an increased charge carrier mobility in the current channel region.Type: GrantFiled: April 8, 2008Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: MeiKei Ieong, Zhibin Ren, Haizhou Yin
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Patent number: 7691688Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.Type: GrantFiled: June 23, 2008Date of Patent: April 6, 2010Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Meikei Ieong, Alexander Reznicek, Devendra K. Sadana, Leathen Shi, Min Yang