Abstract: The present invention relates to a method for treating or alleviating an osteoporosis in a subject. The method comprises steps of identifying the subject having the osteoporosis, and administering to the subject an effective amount of a composition that increases a level of Discoidin Domain Receptor 1 (DDR1) protein in the subject.

Abstract: A pressure sensing module includes a substrate and a sensing layer. The substrate has a first surface and a second surface opposite to each other. The substrate includes a stepped cavity and an opening. The stepped cavity extends from the first surface to the second surface, the opening extends from the second surface to the first surface, and the stepped cavity communicates with the opening. The sensing layer is disposed on the first surface of the substrate and covers the first surface of the substrate. The sensing layer includes at least one sensing element and a cross-shaped structure. The cross-shaped structure includes a central portion and a plurality of extending portions connecting the central portion. The central portion and the extending portions respectively include at least one hollow portion. An orthographic projection of the central portion of the cross-shaped structure on the substrate overlaps with the opening of the substrate.

Abstract: A humanized anti-neurotensin receptor 1 (NTSR1) antibody or an antigen-binding fragment thereof. Also, a method for treating, prophylactic treating and/or preventing diseases and/or disorders caused by or related to NTSR1 activity and/or signaling, and a method or kit for detecting NTSR1 in a sample.

Abstract: A power semiconductor device includes an epitaxial layer of a first conductivity type, a plurality of trench device. The epitaxial layer includes an active region and a termination region. A plurality of trench devices are respectively located in a plurality of device trenches in the epitaxial layer in the active region. A contact metal layer is located on an insulating layer and continuously covering the active region and the termination region. A plurality of termination electrodes are respectively located in a plurality of termination trenches in the epitaxial layer in the termination region and electrically isolated from the epitaxial layer. Each of the plurality of termination electrodes includes a lower electrode and an upper electrode. A first end termination electrode, a second end termination electrode, and a first middle termination electrode of the plurality of termination electrodes are electrically connected to the contact metal layer.

Abstract: A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region. The device electrode is located in a device trench in the active region, and is electrically isolated from the epitaxial layer and the contact metal layer. The first termination electrode is located in a first termination trench in the termination region and is electrically isolated from the epitaxial layer. The second termination electrode is located at a bottom of the first termination trench and is electrically isolated from the first termination electrode and the epitaxial layer. Both the first termination electrode and the second termination electrode are capable of being selectively floating.

Abstract: A sensing module including a circuit substrate, a sensing element, a packaging material and a blocking structure is provided. The sensing element, the packaging material and the blocking structure are disposed on the circuit substrate. The sensing element comprises a sensing portion. The outer side surface of the blocking structure is in direction contact with the packaging material to define a boundary of the packaging material. The sensing portion is disposed in a region encircled by the boundary of the packaging material, and the maximum thickness of the packaging material from a surface facing away from the circuit substrate to the circuit substrate is less than or equal to a distance from the second surface of the blocking structure to the circuit substrate.

Abstract: A variable focal length optical element including a light-transmitting layer, a cover, a gel, a piezoelectric film, and a driving electrode is provided. The cover has a first through hole to define a light-passing area. The cover, an adhesive layer, and the light-transmitting layer surround and form a first cavity together, and the gel is filled in the first cavity. The driving electrode is configured to drive the piezoelectric film, so that the piezoelectric film is deformed to pull the light-transmitting layer to bend and deform to squeeze the gel in the first cavity, and thereby controls a curvature change of an optical surface formed in the light-passing area by the gel protruding out from the first through hole.

Abstract: A power semiconductor device including an epitaxial layer and a fabrication method thereof are provided. A first well region and a second well region separated from each other respectively extend from a surface of the epitaxial layer into the epitaxial layer. A floating doped region is located in the epitaxial layer and between the first well region and the second well region. The floating doped region is separated from the first well region and the second well region. A first doped region and a second doped region respectively extend from the surface of the epitaxial layer into the first well region and the second well region. A gate structure is located on the epitaxial layer and is adjacent to the first doped region and the second doped region. The gate structure is at least partially overlapped with the floating doped region.

Abstract: A power semiconductor device includes an epitaxial layer of a first conductivity type, a first doped region of a second conductivity type, a second doped region of the first conductivity type, a contact metal layer, a device electrode, a first termination electrode, and a second termination electrode. The epitaxial layer includes an active region and a termination region. The device electrode is located in a device trench in the active region, and is electrically isolated from the epitaxial layer and the contact metal layer. The first termination electrode is located in a first termination trench in the termination region and is electrically isolated from the epitaxial layer. The second termination electrode is located at a bottom of the first termination trench and is electrically isolated from the first termination electrode and the epitaxial layer. Both the first termination electrode and the second termination electrode are capable of being selectively floating.

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

Abstract: The present invention provides a method for forming an amorphous silicon multiple layer structure, the method comprises the flowing steps: first, a substrate material layer is provided, next, a first amorphous silicon layer is formed on the substrate material layer, wherein the first amorphous silicon layer includes a plurality of hydrogen atoms disposed therein, afterwards, an UV curing process is performed to the first amorphous silicon layer, so as to remove the hydrogen atoms from the first amorphous silicon layer, finally, a second amorphous silicon layer is formed on the first amorphous silicon layer.

Abstract: The present invention provides a method for fabricating a semiconductor device, comprising at least the steps of: providing a substrate in which a memory region and a peripheral region are defined, the memory region includes a plurality of memory cells, each memory cell includes at least a first transistor and a capacitor, the peripheral region compress a second transistor, a first insulating layer is formed within the memory region and the peripheral region by an atomic layer deposition process, covering the capacitor of the memory cells in the memory region and the second transistor in the peripheral region, and a second insulating layer is formed, overlying the first insulating layer and the peripheral region. Finally, a contact structure is formed within the second insulating layer, and electrically connecting the second transistor.

Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.

Abstract: A semi-vanadium(V) redox flow battery (semi-VRFB) including a positive electrolyte tank, a negative electrolyte tank and a cell stack. The positive electrolyte tank is stored with a positive electrolyte of V ions and the negative electrolyte tank is stored with a negative electrolyte of iodine(I)-vitamin C. The cell stack comprises a positive electrode, a negative electrode, an insulating film, a positive electrode plate, and a negative electrode plate. The negative electrode is made of carbon (C) sandwiched with titanium dioxide(TiO2), and can further comprise a metal or an alloy. The insulating film is located between the positive electrode and the negative electrode. The positive and negative electrode plates are located in front of the positive and negative electrodes, respectively. The positive and negative electrolytes flow through the positive and negative electrode plates to charge/discharge power by the electrochemical reactions of V ions and I-vitamin C at the positive and negative electrodes.

Abstract: A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

Abstract: A MOS P-N junction diode includes a semiconductor substrate, a mask layer, a guard ring, a gate oxide layer, a polysilicon structure, a central conductive layer, a silicon nitride layer, a metal diffusion layer, a channel region, and a metal sputtering layer. For manufacturing the MOS P-N junction diode, a mask layer is formed on a semiconductor substrate. A gate oxide layer is formed on the semiconductor substrate, and a polysilicon structure is formed on the gate oxide layer. A guard ring, a central conductive layer and a channel region are formed in the semiconductor substrate. A silicon nitride layer is formed on the central conductive layer. A metal diffusion layer is formed within the guard ring and the central conductive layer. Afterwards, a metal sputtering layer is formed, and the mask layer is partially exposed.

Abstract: A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.

Abstract: Semiconductor devices, methods of manufacture thereof, and methods of forming conductive features thereof are disclosed. A semiconductor device includes an insulating material layer disposed over a workpiece. The insulating material layer includes a silicon-containing material comprising about 13% or greater of carbon (C). A conductive feature is disposed within the insulating material layer. The conductive feature includes a capping layer disposed on a top surface thereof.

Abstract: A method for fabricating a trench Schottky rectifier device is provided. At first, a plurality of trenched are formed in a substrate of a first conductivity type. An insulating layer is formed on sidewalls of the trenches. Then, an ion implantation procedure is performed through the trenches to form a plurality of doped regions of a second conductivity type under the trenches. Subsequently, the trenches are filled with conductive structure such as metal structure or tungsten structure. At last, an electrode overlying the conductive structure and the substrate is formed. Thus, a Schottky contact appears between the electrode and the substrate. Each doped region and the substrate will form a PN junction to pinch off current flowing toward the Schottky contact to suppress the current leakage in a reverse bias mode.