Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: A tester system includes a test computer system for coordinating and controlling testing of a plurality of devices under test (DUTs) and a hardware interface module coupled to the test computer system and controlled by the test computer system, the hardware interface module operable to apply test input signals to the plurality of DUTs and operable to receive test output signals from the plurality of DUTs. The hardware interface module includes a memory for storing instructions and data, a high performance processor coupled to the memory, the high performance processor operable to perform testing functionality at high speed for application of test signals to the plurality of DUTs, the high performance processor operable to perform the testing functionality under control of instructions and data from the memory and under control from software commands from the test computer system, wherein further the high performance processor is not natively capable of low power mode operation.

Abstract: Disclosed are a super-resolution imaging system (1, 41, 51), a super-resolution imaging method, a biological sample identification system (4, 61) and method, a nucleic acid sequencing imaging system (5) and method, and a nucleic acid identification system (6) and method. The super-resolution imaging system (1, 41, 51) includes an illumination system (A) and an imaging system (B). The illumination system (A) outputs excitation light to irradiate a biological sample to generate excited light, and the imaging system (B) collects and records the excited light to generate an excited light image. The illumination system (A) includes an excitation light source (10, 10a) and a structured light generation and modulation device (11, 11a). The excitation light source (10, 10a) outputs the excitation light, and the structured light generation and modulation device (11, 11a) modulates the excitation light into structured light to irradiate the biological sample to generate the excited light.

Abstract: An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a field programmable gate array (FPGA) communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the device under test (DUT). Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.

Abstract: Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a tester system diagnostic method includes forwarding test signals to a loopback component; receiving the test signals from the loopback component; and analyzing the test signals to diagnose whether or not the test system is experiencing problems associated with electrostatic discharges, including analysis of eye scan configuration data corresponding to characteristics of the test signals. In one exemplary implementation, analyzing the eye scan configuration data, including analyzing symmetry of a graphical representation (e.g., eye pattern, eye diagram, etc.) of the eye scan configuration data with respect to a horizontal graphical representation axis.

Abstract: A JAK kinase inhibitor and use thereof. The JAK kinase inhibitor is a compound represented by formula (I) or a stereoisomer or tautomer thereof or a pharmaceutically acceptable salt thereof or a solvate or prodrug thereof. Further, the use of the compound of formula I in preparation of drugs for preventing or treating JAK kinase-related diseases, especially in preparation of drugs for preventing and/or treating diseases involving cartilage degradation and bone and/or joint degradation, conditions involving inflammation or immune response, endotoxin-driven disease states, cancer, and organ transplantation rejection.

Abstract: The present invention relates to a modulator of 1,2,5-oxadiazole indoleamine-(2,3)-dioxygenase, a preparation method and use thereof, more particularly to compounds of Formula I and Formula II, an isomer thereof, a pharmaceutically acceptable salt or a pharmaceutically acceptable solvate thereof, and their use in preparing drugs for treating cancers, neurodegenerative diseases, eye diseases, mental disorders, depression, anxiety disorders, Alzheimer's diseases and/or autoimmune diseases. Specific meanings of R substituents in Formula I and Formula II are consistent with the description of the specification.

Abstract: A method for selection of a calibration set and a validation set based on spectral similarity and modeling. The method includes: performing NIR spectrometry on original samples to obtain a spectral matrix of the original samples; randomly selecting m samples as an independent test set; calculating spectral similarity between each of the samples in the independent test set and each of the remaining samples in the original samples respectively to obtain g samples having the highest similarity to be written into the validation set; and calculating spectral similarity between each of the samples in the validation set and each of the remaining samples in the original samples respectively to obtain n samples having the highest similarity to be written into the calibration set. Based on the validation set and the calibration set selected through the method, an obtained model can predict unknown samples more accurately.

Abstract: Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a tester system diagnostic method includes forwarding test signals to a loopback component; receiving the test signals from the loopback component; and analyzing the test signals to diagnose whether or not the test system is experiencing problems associated with electrostatic discharges, including analysis of eye scan configuration data corresponding to characteristics of the test signals. In one exemplary implementation, analyzing the eye scan configuration data, including analyzing symmetry of a graphical representation (e.g., eye pattern, eye diagram, etc.) of the eye scan configuration data with respect to a horizontal graphical representation axis.

Abstract: Presented embodiments facilitate efficient and effective flexible implementation of different types of testing procedures in a test system. In one embodiment, a testing system comprises: a loadboard including multiple universal interfaces with the same coupling configuration, a plurality of devices under test (DUTs) including a plurality of DUT interfaces respectively, and a plurality of universal adapters including a plurality of matching universal interfaces that match the plurality of universal interfaces in the loadboard and a plurality of matching DUT interfaces that match the plurality of DUT interfaces in the respective DUT. The plurality of universal adapters are selectively coupled to the loadboard and the plurality of universal adapters are selectively coupled to the DUTs, respectively. A first one of the plurality of DUT interfaces includes a different coupling configuration than a second one of the plurality of DUT interfaces.

Abstract: A method for testing DUT comprises receiving instructions from a system controller at a tester board, wherein the tester board comprises an FPGA and the tester processor are coupled to the system controller, and wherein the tester processor is operable to coordinate testing of a device under test (DUT). The method further comprises generating commands and data for testing the DUT and routing signals associated with the commands and the data in the FPGA based on a type of the DUT. Also, the method comprises transmitting the signals over lanes corresponding to a particular set of pins on the DUT, wherein the particular set of pins depend on the type of the DUT.

Abstract: An automated test equipment (ATE) apparatus comprising a tester processor operable to generate commands and data for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises an FPGA communicatively coupled to the tester processor, wherein the FPGA comprises routing logic operable to route signals associated with the commands and data in the FPGA based on a type of the DUT. Further, the ATE comprises a connector module communicatively coupled to the FPGA comprising a socket to which the DUT connects and further comprising circuitry for routing the signals to a set of pins on the DUT, wherein the set of pins are associated with a first type of DUT. The circuitry can support multiple different DUT types having a common form factor but different pinout assignments.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a primitive configured to control testing of a device under test (DUT) and a device interface board (DIB). The device interface board comprises: a loadboard, an environmental control component and a device under test access interface. The loadboard is configured to selectively couple with a device under test and a primitive. The environmental control component is configured to control environmental conditions. The device under test access interface is configured to allow robotic manipulation of the device under test. The manipulation can include selectively coupling the device under test to the loadboard. The device under test access interface can be configured to enable unobstructed access for robotic manipulation of the device under test.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT, a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: An automated test equipment (ATE) system capable of performing a test of semiconductor devices is presented. The system comprises a first test board including a first FPGA communicatively coupled to a controller via an interface board, wherein the first FPGA comprises a first core programmed to implement a communication protocol, and further wherein the FPGA is programmed with at least one hardware accelerator circuit operable to internally generate commands and data for testing a DUT. The system also includes a second test board comprising a second FPGA communicatively coupled to the first test board, wherein the second FPGA comprises a second core programmed to implement a communication protocol for a device under test, wherein the second FPGA is further programmed to simulate a DUT, and wherein the first FPGA is operable to communicate with the second FPGA in order to test a communication link between the first test board and the second test board.

Abstract: A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

Abstract: An automated test equipment (ATE) system comprises a system controller communicatively coupled to a tester processor, where the system controller is operable to transmit instructions to the tester processor, and where the tester processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The apparatus also comprises an FPGA programmed to support a first protocol communicatively coupled to the tester processor comprising at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing a DUT of the plurality of DUTs. Further, the apparatus comprises a bus adapter comprising a protocol converter module operable to convert signals associated with the first protocol received from the FPGA to signals associated with a second protocol prior to transmitting the signals to the DUT, wherein the DUT communicates using the second protocol.

Abstract: A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.