Abstract: A method for testing using an automated test equipment (ATE) comprises transmitting instructions for executing tests on a device under test (DUT) from a tester processor to a queue communicatively coupled with the tester processor and a Field Programmable Gate Array (FPGA), wherein the tester processor is configured to determine a hardware acceleration mode from a plurality of hardware acceleration modes for executing tests on the DUT. Further, the hardware acceleration mode is configured to distribute functionality for generating commands and data between the tester processor and the FPGA, wherein in at least one hardware acceleration mode the tester processor is configured to generate commands for testing the DUT and the FPGA is configured to generate data for testing the DUT. The method also comprises accessing the instructions in the queue, translating the instructions into commands associated with testing the DUT and transmitting the commands to the DUT.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: The present invention relates to a new pyrrole sulfonyl derivative, and a preparation method and medical use thereof. In particular, the present invention relates to a pyrrole sulfonyl derivative as represented by general formula (I), a preparation method thereof, a pharmaceutical composition comprising the derivative, and a use thereof as a therapeutic agent, in particular as a gastric acid secretion inhibitor and as potassium-competitive acid blockers (P-CABs), wherein each substituent group of general formula (I) is the same as that defined in the description.

Abstract: The present invention relates to a modulator of 1,2,5-oxadiazole indoleamine-(2,3)-dioxygenase, a preparation method and use thereof, more particularly to compounds of Formula I and Formula II, an isomer thereof, a pharmaceutically acceptable salt or a pharmaceutically acceptable solvate thereof, and their use in preparing drugs for treating cancers, neurodegenerative diseases, eye diseases, mental disorders, depression, anxiety disorders, Alzheimer's diseases and/or autoimmune diseases. Specific meanings of R substituents in Formula I and Formula II are consistent with the description of the specification.

Abstract: An image sensor module comprises: a substrate having a first side and second side, the first side being an opposite of the second side, an image sensor attached to the first side of the substrate, bonding wires to bond the image sensor to pads on the first side of the substrate, a protective structure disposed on the first side of the substrate surrounding the image sensor, the bonding wires, and the pads, the protective structure having a dam and a lid, a cover glass disposed on the protective structure, and a set of solder balls attached to the second side of the substrate.

Abstract: The application discloses five polymorph forms B, P, F, J, O of (4-((R)-((2S,5R)-4-(3-fluorobenzyl)-(2,5-dimethylpiperazine-1-yl)(3-hydroxyphenyl)methyl)phenyl)(4-methylpiperidine-1-yl)methanone dihydrochloride, preparation methods thereof and application thereof in the manufacture of a medicament for preventing or treating a mood disorder or a disease related to a ? opioid receptor.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes a controller processor; a plurality of programmable accelerator circuits coupled to and controlled by the controller processor; and a plurality of load boards respectively coupled to the plurality of programmable accelerator circuits. The plurality of load boards can apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. The plurality of programmable accelerator circuits can provide input test signals and capture output test signals. In one exemplary implementation, each of the plurality of load boards comprises: a first set of connections for transmitting input test signals to a respective DUT; a second set of connections for receiving output test signals from the respective DUT; and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: The present invention facilitates efficient and effective device testing and debugging. In one embodiment, a tester system includes: a controller processor, a plurality of programmable accelerator circuits, and a plurality of load boards respectively. The plurality of programmable accelerator circuits providing input test signals and capture output test signals. The plurality of load boards apply the input test signals to a plurality of devices under test (DUTs) and capture the output test signals therefrom. In one exemplary implementation, each of the plurality of load boards includes a first set of connections that transmit input test signals to a respective DUT,a second set of connections that receive output test signals from the respective DUT, and sideband connectors. The sideband connectors receive test related information from the DUT.

Abstract: A method for diagnosing a root cause of failure using automated test equipment is disclosed. The method comprises monitoring data traffic associated with testing a device under test (DUT) in the automated test equipment using a plurality capture modules, wherein the plurality of capture modules are programmed onto a programmable logic device, wherein the programmable logic device is controlled by a system controller and is operable to generate commands and data to test the DUT, wherein the plurality of capture modules are operable to selectively capture the data traffic to be monitored, and wherein the data traffic monitored comprises a flow of traffic between the DUT and the system controller. The method further comprises saving results associated with the monitoring in respective memories associated with each of the plurality of capture modules. Further, the method comprises transmitting the results upon request to an application program executing on the system controller.

Abstract: A method for diagnosing a root cause of failure using automated test equipment (ATE) is disclosed. The method comprises identifying a failing device under test (DUT). Further, the method comprises opening a test program log associated with the failing DUT and determining a time of failure by parsing through the test program log to find an identifier and timestamp associated with the failure. Finally, the method comprises displaying the test program log in a window within a graphical user interface, wherein a relevant section of the test program log associated with the failure is displayed in the window.

Abstract: A scalable test platform can include one or more of a plurality of different device interface boards and a plurality of primitives. The different device interface boards can be configured to provide a uniform interface to couple different types of DUTs and or DUTs with different form factors to the plurality of primitives. The plurality of primitives can be configured to distribute power to the DUTs, and to perform system level testing of the respective DUTs. The plurality of primitives can be configurable by a user to perform any number of system level tests on a number of different types of DUTs and or DUTs with different form factors.

Abstract: The application discloses five polymorph forms B, P, F, J, O of (4-((R)-((2S,5R)-4-(3-fluorobenzyl)-(2,5-dimethylpiperazine-1-yl)(3-hydroxyphenyl)methyl)phenyl)(4-methylpiperidine-1-yl)methanone dihydrochloride, preparation methods thereof and application thereof in the manufacture of a medicament for preventing or treating a mood disorder or a disease related to a ? opioid receptor.

Abstract: The invention relates to a 4-substituted pyrrolo[2,3-d]pyrimidine compound and the use thereof in preparing medications for treating JAK-targeted diseases such as rheumatoid, immune system diseases, and tumor. The 4-substituted pyrrolo[2,3-d]pyrimidine compound of the invention is as shown in chemical formula I. The activity experimental results of the invention show that the new compound has obvious effect and activity in inhibition of Janus kinases, JAK-STAT, cell proliferation of human lymphocytoma, and rheumatoid arthritis.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: An image sensor module comprises: a substrate having a first side and second side, the first side being an opposite of the second side, an image sensor attached to the first side of the substrate, bonding wires to bond the image sensor to pads on the first side of the substrate, a protective structure disposed on the first side of the substrate surrounding the image sensor, the bonding wires, and the pads, the protective structure having a dam and a lid, a cover glass disposed on the protective structure, and a set of solder balls attached to the second side of the substrate.

Abstract: Automated test equipment (ATE) capable of performing a test of semiconductor devices is presented. The ATE comprises a computer system comprising a system controller communicatively coupled to a tester processor. The system controller is operable to transmit instructions to the processor and the processor is operable to generate commands and data from the instructions for coordinating testing of a plurality of devices under test (DUTs). The ATE further comprises a plurality of FPGA components communicatively coupled to the processor via a bus. Each of the FPGA components comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the processor for testing one of the DUTs. Additionally, the tester processor is configured to operate in one of several functional modes, wherein the functional modes are configured to allocate functionality for generating commands and data between the processor and the FPGA components.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a device interface board (DIB) configured to interface with a device under test (DUT); and a primitive configured to control the device interface board and testing of the device under test. The primitive is an independent self contained test control unit comprising: a backplane interface configured to couple with the device interface board; a power supply component configured to control power to the backplane interface; and a site module configured to control testing signals sent to the device interface board and device under test. The site module is reconfigurable for different test protocols. The primitive can be compatible with a distributed testing infrastructure. In one exemplary implementation, the primitive and device interface board are portable an operable to perform independent testing unfettered by other control components.

Abstract: An automated test equipment (ATE) apparatus is presented. The apparatus comprises a computer system comprising a system controller, wherein the system controller is communicatively coupled to a site module board comprising a tester processor and an FPGA wherein the system controller is operable to transmit instructions to the tester processor, and wherein the tester processor is operable to generate commands and data from the instructions for coordinating testing of a device under test (DUT) wherein the site module board comprises a compact form factor suitable for use during prototyping, and wherein the site module board is operable to be coupled with a DUT. Further, the FPGA is communicatively coupled to the tester processor, wherein the FPGA comprises at least one hardware accelerator circuit operable to internally generate commands and data transparently from the tester processor for testing the DUT.

Abstract: Presented embodiments facilitate efficient and effective access to a device under test. In one embodiment, a test system comprises: a primitive configured to control testing of a device under test (DUT) and a device interface board (DIB). The device interface board comprises: a loadboard, an environmental control component and a device under test access interface. The loadboard is configured to selectively couple with a device under test and a primitive. The environmental control component is configured to control environmental conditions. The device under test access interface is configured to allow robotic manipulation of the device under test. The manipulation can include selectively coupling the device under test to the loadboard. The device under test access interface can be configured to enable unobstructed access for robotic manipulation of the device under test.