Abstract: The present disclosure discloses a tobacco leaf foliar spraying substance for reducing harmful ingredients in cheroot, a method for reducing carcinogenic components in flue-cured tobacco leaves and flue-cured tobacco shreds. The tobacco leaf foliar spraying substance contains a lotus leaf extract, the harmful chemical ingredients comprise N-nitrosonornicotine, 4-(N-methyl-nitrosamine)-1-(3-pyridinyl)-1-butanone, N-nitrosoanabasine and N-nitrosoanatabine. Foliar spraying is performed on a fertile field by using the lotus leaf extract before tobacco leaves are harvested and modulated, which not only significantly promotesagronomic characters and economic traits of tobacco and alleviates tobacco leaf browning but also effectively reduces harmful chemical ingredients unique to tobacco leaves, such as nitrosamine and nicotine.

Abstract: An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

Abstract: A method includes forming isolations extending into a semiconductor substrate, recessing the isolation regions, wherein a semiconductor region between the isolation regions forms a semiconductor fin, forming a first dielectric layer on the isolation regions and the semiconductor fin, forming a second dielectric layer over the first dielectric layer, planarizing the second dielectric layer and the first dielectric layer, and recessing the first dielectric layer. A portion of the second dielectric layer protrudes higher than remaining portions of the first dielectric layer to form a protruding dielectric fin. A portion of the semiconductor fin protrudes higher than the remaining portions of the first dielectric layer to form a protruding semiconductor fin. A portion of the protruding semiconductor fin is recessed to form a recess, from which an epitaxy semiconductor region is grown. The epitaxy semiconductor region expands laterally to contact a sidewall of the protruding dielectric fin.

Abstract: Epitaxial source/drain structures for enhancing performance of multigate devices, such as fin-like field-effect transistors (FETs) or gate-all-around (GAA) FETs, and methods of fabricating the epitaxial source/drain structures, are disclosed herein. An exemplary device includes a dielectric substrate. The device further includes a channel layer, a gate disposed over the channel layer, and an epitaxial source/drain structure disposed adjacent to the channel layer. The channel layer, the gate, and the epitaxial source/drain structure are disposed over the dielectric substrate. The epitaxial source/drain structure includes an inner portion having a first dopant concentration and an outer portion having a second dopant concentration that is less than the first dopant concentration. The inner portion physically contacts the dielectric substrate, and the outer portion is disposed between the inner portion and the channel layer. In some embodiments, the outer portion physically contacts the dielectric substrate.

Abstract: Disclosed is a recycled polystyrene (PS) plastic film prepared from 100% of a waste PS plastic or prepared from a waste PS plastic and a modification material, where a content of the waste PS plastic is greater than or equal to 1% and less than 100% and a content of the modification material is greater than 0% and less than or equal to 99%. The preparation of the recycled PS plastic film with the waste PS plastic can save resources. In addition, the waste PS plastic is modified by the modification material to improve the performance of the plastic, which is conducive to preparation of an acousto-magnetic (AM) anti-theft label housing with excellent performance. Also disclosed are a preparation method of the recycled PS plastic film, an AM anti-theft label housing made of the recycled PS plastic film and a preparation method thereof, and a corresponding AM anti-theft label.

Abstract: A di(2-ethylhexyl) terephthalate composition is provided. The di(2-ethylhexyl) terephthalate composition comprises di(2-ethylhexyl)terephthalate, at least one of a first component, a second component and a third component, and a fourth component When the di(2-ethylhexyl) terephthalate composition is characterized by gas chromatography (GC), the first component is eluted at a retention time ranging from 4.8 minutes to 6.0 minutes, the second component is eluted at a retention time ranging from 9.0 minutes to 10.0 minutes, the third component is eluted at a retention time ranging from 10.1 minutes to 12.0 minutes, and the fourth component is eluted at a retention time ranging from 21.0 minutes to 22.1 minutes. The ratio of the total area of the chromatographic peaks indicating the first component, second component, and third component to the area of the chromatographic peaks indicating the fourth component is 0.135 to 1.720.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: Disclosed herein are humanized antibodies, antigen-binding fragments thereof, and antibody conjugates, that are capable of specifically binding to certain biantennary Lewis antigens, which antigens are expressed in a variety of cancers. The presently disclosed antibodies are useful to target antigen-expressing cells for treatment or detection of disease, including various cancers. Also provided are polynucleotides, vectors, and host cells for producing the disclosed antibodies and antigen-binding fragments thereof. Pharmaceutical compositions, methods of treatment and detection, and uses of the antibodies, antigen-binding fragments, antibody conjugates, and compositions are also provided.

Abstract: An upper extremity wearable device includes a pressure sleeve configure to wrap a forearm, a middle finger stimulating electrode and a ring finger stimulating electrode disposed on an inner surface of the pressure sleeve. The middle finger stimulating electrode covers a middle finger stimulating point which is measured from an ulnar styloid process, moving two lateral units, and moving four longitudinal units. The ring finger stimulating electrode covers a ring finger stimulating point which is measured from the ulnar styloid process, moving one lateral unit, and moving five longitudinal units. The lateral unit is a distance from the position of the pressure sleeve corresponding to the ulnar styloid process to a radial styloid process dividing four. The longitudinal unit is a distance from the position of the pressure sleeve corresponding to the ulnar styloid process to an olecranon process dividing twelve.

Abstract: A device includes first and second semiconductor fins, first, second, third and fourth fin sidewall spacers, and first and second epitaxy structures. The first and second fin sidewall spacers are respectively on opposite sides of the first semiconductor fin. The third and fourth fin sidewall spacers are respectively on opposite sides of the second semiconductor fin. The first and third fin sidewall spacers are between the first and second semiconductor fins and have smaller heights than the second and fourth fin sidewall spacers. The first and second epitaxy structures are respectively on the first and second semiconductor fins and merged together.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a lead frame and a sub-substrate disposed on the lead frame, wherein the thickness of the sub-substrate is between 0 and 0.5 ?m. The semiconductor structure also includes an epitaxial layer disposed on the sub-substrate. The epitaxial layer includes a buffer layer, a channel layer and a barrier layer. The buffer layer is disposed between the sub-substrate and the channel layer. The channel layer is disposed between the buffer layer and the barrier layer. The semiconductor structure further includes a device layer disposed on the barrier layer and an interconnector structure electrically connected to the epitaxial layer and/or the device layer by a through hole.

Abstract: The invention relates to a method, an apparatus and a computer program product for reading data from multiple flash dies. The method is performed by a processing unit when loading and executing program code to include: issuing a read instruction to a flash interface to drive the flash interface to activate a data read operation for reading data from a location in a die; calculating an output time point corresponding to the read instruction; and issuing a random out instruction corresponding to the read instruction to the flash interface to drive the flash interface to store the data in a random access memory (RAM) when a current time reaches to, or is later than the output time point.

Abstract: A method for manufacturing a package structure includes providing a carrier board; providing at least one die having a top surface, a bottom surface, and a side surface on the carrier board; and forming a protective layer to cover at least a portion of the side surface of the die. The die includes a substrate, a semiconductor layer, a gate structure, a source structure and a drain structure, at least one dielectric layer, and at least one pad. The semiconductor layer is disposed on the substrate. The gate structure is disposed on the semiconductor layer. The source and the drain structures are disposed on opposite sides of the gate structure. The dielectric layer covers the gate, source, and drain structures. The pad is disposed on the dielectric layer and penetrates through the dielectric layer to electrically contact with the gate, source or drain structure.

Abstract: A chip structure includes a substrate, a bottom conductive layer, a semiconductor layer, an interlayer dielectric layer, at least one electrode, and at least one top electrode. The substrate includes in order a core layer and a composite material. The bottom conductive layer is disposed on the bottom surface of the core layer, the semiconductor layer is disposed on the substrate, and an interlayer dielectric layer is disposed on the semiconductor layer. The at least one electrode is disposed between the semiconductor layer and the interlayer dielectric layer, and the at least one top electrode is disposed on the interlayer dielectric layer and electrically coupled to the at least one electrode.

Abstract: A di(2-ethylhexyl) terephthalate composition is provided. The di(2-ethylhexyl) terephthalate composition comprises di(2-ethylhexyl)terephthalate, at least one of a first component, a second component and a third component, and a fourth component When the di(2-ethylhexyl) terephthalate composition is characterized by gas chromatography (GC), the first component is eluted at a retention time ranging from 4.8 minutes to 6.0 minutes, the second component is eluted at a retention time ranging from 9.0 minutes to 10.0 minutes, the third component is eluted at a retention time ranging from 10.1 minutes to 12.0 minutes, and the fourth component is eluted at a retention time ranging from 21.0 minutes to 22.1 minutes. The ratio of the total area of the chromatographic peaks indicating the first component, second component, and third component to the area of the chromatographic peaks indicating the fourth component is 0.135 to 1.720.

Abstract: A system for eliminating interference of randomly stacked workpieces is disclosed. The system includes a three-dimensional sensing module, a pick-up apparatus and a control module. The control module is coupled to the three-dimensional sensing module and the pick-up apparatus. The control module is configured to control the three-dimensional sensing module to capture a three-dimensional image, analyze the three-dimensional image to obtain an image information, select a target workpiece to be picked up according to the image information, arrange an interference elimination path for the target workpiece, and control the pick-up apparatus to eliminate interference of the target workpiece according to the interference elimination path.

Abstract: A method of forming dice includes the following steps. First, a wafer structure is provides, which includes a substrate and a stack of semiconductor layers disposed in die regions and a scribe line region. Then, the substrate and the stack of the semiconductor layers in the scribe line region are removed to form a groove in the substrate. After the formation of the groove, the substrate is further thinned to obtain the substrate with a reduced thickness. Finally, a separation process is performed on the substrate with the reduced thickness.

Abstract: The invention relates to a method, an apparatus and a computer program product for reading data from multiple flash dies. The method is performed by a processing unit when loading and executing program code to include: issuing a read instruction to a flash interface to drive the flash interface to activate a data read operation for reading data from a location in a die; calculating an output time point corresponding to the read instruction; and issuing a random out instruction corresponding to the read instruction to the flash interface to drive the flash interface to store the data in a random access memory (RAM) when a current time reaches to, or is later than the output time point.