Patents by Inventor Meikei Ieong
Meikei Ieong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6960806Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and ?0.5V for pFETs.Type: GrantFiled: June 21, 2001Date of Patent: November 1, 2005Assignee: International Business Machines CorporationInventors: Andres Bryant, Meikei Ieong, K. Paul Muller, Edward J. Nowak, David M. Fried, Jed Rankin
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Publication number: 20050236687Abstract: Methods of forming a strained Si-containing hybrid substrate are provided as well as the strained Si-containing hybrid substrate formed by the methods. In the methods of the present invention, a strained Si layer is formed overlying a regrown semiconductor material, a second semiconducting layer, or both. In accordance with the present invention, the strained Si layer has the same crystallographic orientation as either the regrown semiconductor layer or the second semiconducting layer. The methods provide a hybrid substrate in which at least one of the device layers includes strained Si.Type: ApplicationFiled: April 22, 2004Publication date: October 27, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kevin Chan, Bruce Doris, Kathryn Guarini, Meikei Ieong, Shreesh Narasimha, Alexander Reznicek, Kern Rim, Devendra Sadana, Leathen Shi, Jeffrey Sleight, Min Yang
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Publication number: 20050221543Abstract: Accordingly, the present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention uses provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping on of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. In particular, by asymmetrically doping the two gates, the resulting transistor can, with adequate doping of the body, have a threshold voltage in a range that enables low-voltage CMOS operation. For example, a transistor can be created that has a threshold voltage between 0V and 0.5V for nFETs and between 0 and ?0.5V for pFETs.Type: ApplicationFiled: May 9, 2005Publication date: October 6, 2005Inventors: Andres Bryant, Meikei Ieong, K. Muller, Edward Nowak, David Fried, Jed Rankin
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Patent number: 6946696Abstract: A double-gate field effect transistor (DGFET) structure and method of forming such a structure in which the parasitic capacitance under the source/drain regions is substantially reduced are provided. Two new means to reduce the parasitic capacitance under the source/drain regions are provided. Firstly, the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer. The oxidation can be facilitated using a self-aligned oxygen implant, or implant of some other species. Secondly, the first spacer is removed, replaced with a second spacer, and a new silicon source/drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed, over the self-aligned oxide isolation region. This achieves a low-capacitance to the back-plane, while retaining control of the threshold voltages.Type: GrantFiled: December 23, 2002Date of Patent: September 20, 2005Assignee: International Business Machines CorporationInventors: Kevin K. Chan, Guy M. Cohen, Meikei Ieong, Ronnen A. Roy, Paul Solomon, Min Yang
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Publication number: 20050164433Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.Type: ApplicationFiled: March 18, 2005Publication date: July 28, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce Doris, Thomas Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong, Omer Dokumaci
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Patent number: 6916698Abstract: High performance (surface channel) CMOS devices with a mid-gap work function metal gate are disclosed wherein an epitaxial layer is used for a threshold voltage Vt adjust/decrease for the PFET area, for large Vt reductions (˜500 mV), as are required by CMOS devices with a mid-gap metal gate. The present invention provides counter doping using an in situ B doped epitaxial layer or a B and C co-doped epitaxial layer, wherein the C co-doping provides an additional degree of freedom to reduce the diffusion of B (also during subsequent activation thermal cycles) to maintain a shallow B profile, which is critical to provide a surface channel CMOS device with a mid-gap metal gate while maintaining good short channel effects. The B diffusion profiles are satisfactorily shallow, sharp and have a high B concentration for devices with mid-gap metal gates, to provide and maintain a thin, highly doped B layer under the gate oxide.Type: GrantFiled: March 8, 2004Date of Patent: July 12, 2005Assignee: International Business Machines CorporationInventors: Anda C. Mocuta, Meikei Ieong, Ricky S. Amos, Diane C. Boyd, Dan M. Mocuta, Huajie Chen
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Publication number: 20050145837Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a <110> crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing <110> layer; and creating a biaxial strain in the silicon-containing <110> layer.Type: ApplicationFiled: November 3, 2004Publication date: July 7, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Massimo Fischetti, John Hergenrother, Meikei Ieong, Rajesh Rengarajan, Alexander Reznicek, Paul Solomon, Chun-yung Sung, Min Yang
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Patent number: 6914303Abstract: Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.Type: GrantFiled: August 28, 2003Date of Patent: July 5, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas S. Kanarsky, Ying Zhang, Huilong Zhu, Meikei Ieong, Omer Dokumaci
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Patent number: 6911383Abstract: The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.Type: GrantFiled: June 26, 2003Date of Patent: June 28, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Diane C. Boyd, Meikei Ieong, Thomas S. Kanarsky, Jakub T. Kedzierski, Min Yang
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Publication number: 20050127408Abstract: Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.Type: ApplicationFiled: December 16, 2003Publication date: June 16, 2005Inventors: Bruce Doris, Meikei Ieong, Thomas Kanarsky
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Publication number: 20050127362Abstract: A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.Type: ApplicationFiled: December 10, 2003Publication date: June 16, 2005Inventors: Ying Zhang, Bruce Doris, Thomas Kanarsky, Meikei Ieong, Jakub Kedzierski
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Patent number: 6905941Abstract: A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.Type: GrantFiled: June 2, 2003Date of Patent: June 14, 2005Assignee: International Business Machines CorporationInventors: Bruce B. Doris, Thomas S. Kanarsky, Meikei Ieong, Wesley C. Natzle
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Publication number: 20050118826Abstract: The present invention comprises a method for forming an ultra-thin channel MOSFET and the ultra-thin channel MOSFET produced therefrom. Specifically, the method comprises providing an SOI substrate having a buried insulating layer underlying an SOI layer; forming a pad stack atop the SOI layer; forming a block mask having a channel via atop the pad stack; providing a localized oxide region in the SOI layer on top of the buried insulating layer thereby thinning a portion of the SOI layer, the localized oxide region being self-aligned with the channel via; forming a gate in the channel via; removing at least the block mask; and forming source/drain extensions in the SOI layer abutting the thinned portion of the SOI layer. Providing the localized oxide region further comprises implanting oxygen dopant through the channel via into a portion of the SOI layer; and annealing the dopant to create the localized oxide region.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane Boyd, Bruce Doris, Meikei Ieong, Devendra Sadana
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Publication number: 20050116289Abstract: The present invention provides a thin channel MOSFET having low external resistance. In broad terms, a silicon-on-insulator structure comprising a SOI layer located atop a buried insulating layer, said SOI layer having a channel region which is thinned by the presence of an underlying localized oxide region that is located on top of and in contact with said buried insulating layer; and a gate region located atop said SOI layer, wherein said localized oxide region is self-aligned with the gate region. A method for forming the inventive MOSFET is also provided comprising forming a dummy gate region atop a substrate; implanting oxide forming dopant through said dummy gate to create a localized oxide region in a portion of the substrate aligned to the dummy gate region that thins a channel region; forming source/drain extension regions abutting said channel region; and replacing the dummy gate with a gate conductor.Type: ApplicationFiled: December 2, 2003Publication date: June 2, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Diane Boyd, Bruce Doris, Meikei Ieong, Devendra Sadana
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Publication number: 20050093077Abstract: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive or insulating interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.Type: ApplicationFiled: March 12, 2004Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Meikei Ieong, Alexander Reznicek, Min Yang
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Publication number: 20050093104Abstract: A method in which semiconductor-to-semiconductor direct wafer bonding is employed to provide a hybrid substrate having semiconductor layers of different crystallographic orientations that are separated by a conductive interface is provided. Also provided are the hybrid substrate produced by the method as well as using the direct bonding method to provide an integrated semiconductor structure in which various CMOS devices are built upon a surface orientation that enhances device performance.Type: ApplicationFiled: October 29, 2003Publication date: May 5, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Meikei Ieong, Alexander Reznicek, Min Yang
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Publication number: 20050067620Abstract: Three-dimensional (3D) integration schemes of fabricating a 3D integrated circuit in which the pFETs are located on an optimal crystallographic surface for that device and the nFETs are located on a optimal crystallographic surface for that type of device are provided. In accordance with a first 3D integration scheme of the present invention, first semiconductor devices are pre-built on a semiconductor surface of a first silicon-on-insulator (SOI) substrate and second semiconductor devices are pre-built on a semiconductor surface of a second SOI substrate. After pre-building those two structures, the structure are bonded together and interconnect through wafer-via through vias.Type: ApplicationFiled: August 9, 2004Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Victor Chan, Kathryn Guarini, Meikei Ieong
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Publication number: 20050070077Abstract: The present invention provides integrated semiconductor devices that are formed upon an SOI substrate having different crystal orientations that provide optimal performance for a specific device. Specifically, an integrated semiconductor structure including at least an SOI substrate having a top semiconductor layer of a first crystallographic orientation and a semiconductor material of a second crystallographic orientation, wherein the semiconductor material is substantially coplanar and of substantially the same thickness as that of the top semiconductor layer and the first crystallographic orientation is different from the second crystallographic orientation is provided. The SOI substrate is formed by wafer bonding, ion implantation and annealing.Type: ApplicationFiled: October 18, 2004Publication date: March 31, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kathryn Guarini, Meikei Ieong, Leathen Shi, Min Yang
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Publication number: 20050064636Abstract: A method of fabricating complementary metal oxide semiconductor (CMOS) field effect transistors which includes selective doping and full silicidation of a polysilicon material comprising the gate electrode of the transistor. In one embodiment, prior to silicidation, the polysilicon is amorphized. In a further embodiment, siliciding is performed at a low substrate temperature.Type: ApplicationFiled: September 24, 2003Publication date: March 24, 2005Inventors: Cyril Cabral, Meikei Ieong, Jakub Kedzierski
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Publication number: 20050059252Abstract: A double-gate transistor has front (upper) and back gates aligned laterally by a process of forming symmetric sidewalls in proximity to the front gate and then oxidizing the back gate electrode at a temperature of at least 1000 degrees for a time sufficient to relieve stress in the structure, the oxide penetrating from the side of the transistor body to thicken the back gate oxide on the outer edges, leaving an effective thickness of gate oxide at the center, aligned with the front gate electrode. Optionally, an angled implant from the sides of an oxide enhancing species encourages relatively thicker oxide in the outer implanted areas and an oxide-retarding implant across the transistor body retards oxidation in the vertical direction, thereby permitting increase of the lateral extent of the oxidation.Type: ApplicationFiled: September 15, 2003Publication date: March 17, 2005Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Omer Dokumaci, Bruce Doris, Kathryn Guarini, Suryanarayan Hegde, MeiKei Ieong, Erin Jones