Patents by Inventor Meiling Wang

Meiling Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190124571
    Abstract: Embodiments of the present disclosure provide a scheduling method and a base station. In a cell handover process, a target base station serving a target cell receives a random access request from a terminal, sends a random access response to the terminal according to the random access request, and proactively sends an uplink grant to the terminal after sending the random access response and prior to receiving a handover complete command from the terminal. By proactively sending the uplink grant, the target base station can perform uplink scheduling for UE before cell handover is completed, so as to reduce an uplink transmission latency caused by the cell handover.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Xiangzhen KONG, Lian LI, Chao QIN, Meiling WANG, Jiao ZHENG
  • Publication number: 20170325700
    Abstract: Real-time vagal monitoring and intervention is provided. An exemplary system for real-time vagal monitoring and intervention may include a monitor device. Such a monitor device may include one or more electrocardiograph (ECG) electrodes that detects electrical activity in a heart of the person, a processor that executes instructions to calculate multiple measures of heart rate variability (HRV) based on electrical activity detected by the ECG electrodes, and a wireless interface that continuously transmits each calculated HRV measure over a wireless network to a user device.
    Type: Application
    Filed: October 16, 2015
    Publication date: November 16, 2017
    Inventors: Richard LANE, Janet Meiling WANG, John ALLEN
  • Publication number: 20150263972
    Abstract: The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.
    Type: Application
    Filed: May 13, 2015
    Publication date: September 17, 2015
    Inventors: Ahmed Louri, Janet Meiling Wang Roveda, Avinash K. Kodi, Ashwini Sarathy
  • Publication number: 20140247689
    Abstract: Hydrogen molecule (H2) has been indicated as a novel anti-oxidant reagent specifically targeting OH free radicals. This invention discloses the methods and apparatus that can be used to increase the hydrogen concentration in water, in beverages, and in other hydrogen absorbing materials through a sealed hydrogen gas producing chamber made of materials that have good hydrogen permeability and can withhold gas pressure. The disclosed method and apparatus can increase the hydrogen concentration quickly without leaking other chemical by-products of the gas producing system into the treated materials.
    Type: Application
    Filed: January 23, 2014
    Publication date: September 4, 2014
    Applicant: Centaqua Inc.
    Inventors: Meiling Wang, Lili Huang
  • Patent number: 8005660
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: August 23, 2011
    Assignee: Anova Solutions, Inc.
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Publication number: 20110191646
    Abstract: The present invention provides methods for detecting and correcting transmission errors in inter-router links of Network-on-Chip (NoC) architectures. A NoC has repeaters along its bus lines. The output of a main repeater is compared and multiplexed with the output of a shadow repeater. If these outputs are the same the multiplexer outputs the output of the main repeater, otherwise an error is detected and the multiplexer outputs the output of the shadow repeater.
    Type: Application
    Filed: April 6, 2009
    Publication date: August 4, 2011
    Applicants: on behalf of the University of Arizona, Ohio University
    Inventors: Ahmed Louri, Janet Meiling Wang Roveda, Avinash K. Kodi, Ashwini Sarathy
  • Publication number: 20100002581
    Abstract: The present invention provides methods for connecting routers and transmitting data along inter-router links within Nework-on-Chip (NoC) architectures.
    Type: Application
    Filed: April 6, 2009
    Publication date: January 7, 2010
    Applicant: The Arizona Board of Regents on Behalf of The University of Arizona
    Inventors: Ahmed Louri, Janet Meiling Wang Roveda, Avinash K. Kodi, Ashwini Sarathy
  • Publication number: 20080059143
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). A hierarchical SAP process breaks an overall circuit into a plurality of subcircuits and performs circuit simulation and SAP analysis steps on each subcircuit. An integration and reduction process combines the analysis results of each subcircuit, and a final SPICE/SAP process provides a model for the overall circuit based on the subcircuits.
    Type: Application
    Filed: June 27, 2007
    Publication date: March 6, 2008
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Patent number: 7243320
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.
    Type: Grant
    Filed: December 12, 2005
    Date of Patent: July 10, 2007
    Assignee: Anova Solutions, Inc.
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Publication number: 20060150129
    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces the large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance metrics to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.
    Type: Application
    Filed: December 12, 2005
    Publication date: July 6, 2006
    Inventors: Hsien-Yen Chiu, Meiling Wang, Jun Li
  • Publication number: 20050287205
    Abstract: A dietary supplement composition, dosage forms, and methods of use are provided which comprise an effective amount of at least one compound selected from the group consisting of acetic acid, citric acid, and malic acid; and, at least one carrier selected from the group consisting of a cyclodextrin, a porous starch, a KONJAC powder, and a carboxyl methyl cellulose (CMC).
    Type: Application
    Filed: June 22, 2005
    Publication date: December 29, 2005
    Inventors: Meiling Wang, Zhuying Wang, Fangliang Zhang, Luquan Wang