Abstract: A touch display panel including an active device array substrate, a display medium and an opposite substrate is provided. The active device array substrate includes a substrate, a pixel array and a touch sensing layer. The pixel array is disposed on the substrate. The touch sensing layer includes a plurality of first sensing pads disposed on the pixel array and a plurality of bridge conductors embedded in the pixel array. The first sensing pads and the bridge conductors are electrically connected so as to form a plurality of first sensing series.

Abstract: A touch display panel including an active device array substrate, a display medium and an opposite substrate is provided. The active device array substrate includes a substrate, a pixel array and a touch sensing layer. The pixel array is disposed on the substrate. The touch sensing layer includes a plurality of first sensing pads disposed on the pixel array and a plurality of bridge conductors embedded in the pixel array. The first sensing pads and the bridge conductors are electrically connected so as to form a plurality of first sensing series.

Abstract: The invention discloses a liquid crystal display apparatus and a color filter substrate. The color filter substrate can be used in a display module. The color filter substrate may include a glass substrate, a light-shielding matrix, a color layer and one or multiple transparent conductive films disposed on the same side of the glass substrate. There is at least one slit structure formed on one of the transparent conductive films. Each slit structure corresponds to the color layer respectively. The one or multiple transparent conductive films can be used for shielding a liquid crystal layer of the display module.

Abstract: A pixel structure of a display panel includes a substrate, a thin film transistor (TFT), a first transparent connecting pad, a passivation layer and a transparent pixel electrode. The TFT disposed on the substrate includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer is disposed on the gate electrode, the semiconductor layer is disposed on the gate insulating layer, and the source electrode and the drain electrode are disposed on the semiconductor layer. The first transparent connecting pad disposed on the drain electrode partially overlaps and is electrically connected to the drain electrode. The passivation layer disposed on the first transparent connecting pad includes at least a contact hole. Furthermore, the transparent pixel electrode disposed on the passivation layer is electrically connected to the first transparent connecting pad through the contact hole of the passivation layer.

Abstract: The present invention provides a pixel structure including a substrate, a common line, a first transparent electrode, an insulating layer, a drain, and a second transparent electrode. The common line is disposed on the substrate, and the first transparent electrode is disposed on the substrate and the common line and electrically connected to the common line. The insulating layer covers the substrate and the first transparent electrode, and the drain is disposed on the insulating layer. The second transparent electrode is disposed on the insulating layer and overlaps the first transparent electrode, and the second transparent electrode is in contact with the drain.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. A common electrode is disposed on the substrate to surround each of the pixel areas. A capacitance storage electrode is disposed on the common electrode. A first passivation layer covers the capacitance storage electrode and the common electrode. A gate insulation layer covers the scan line and the gate electrode. A semiconductor layer is disposed on the gate insulation layer. A data line, a source and a drain are disposed in each of the pixel areas and the source and the drain are disposed on two sides of the semiconductor layer. A second passivation layer has a contact window and covers the data line, the source, and the drain. A pixel electrode is disposed in each of the pixel areas and is electrically connected with the drain through the contact window.

Abstract: A pixel structure of a display panel includes a substrate, a thin film transistor (TFT), a first transparent connecting pad, a passivation layer and a transparent pixel electrode. The TFT disposed on the substrate includes a gate electrode, a gate insulating layer, a semiconductor layer, a source electrode and a drain electrode. The gate insulating layer is disposed on the gate electrode, the semiconductor layer is disposed on the gate insulating layer, and the source electrode and the drain electrode are disposed on the semiconductor layer. The first transparent connecting pad disposed on the drain electrode partially overlaps and is electrically connected to the drain electrode. The passivation layer disposed on the first transparent connecting pad includes at least a contact hole. Furthermore, the transparent pixel electrode disposed on the passivation layer is electrically connected to the first transparent connecting pad through the contact hole of the passivation layer.

Abstract: A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is disposed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is disposed on the gate insulation layer above the gate electrode. The source and the drain are disposed on two sides of the semiconductor layer. A passivation layer is disposed on the substrate to cover the data line, the source and the drain. The passivation layer above the drain has a contact window. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: The invention discloses a liquid crystal display apparatus and a color filter substrate. The color filter substrate can be used in a display module. The color filter substrate may include a glass substrate, a light-shielding matrix, a color layer and one or multiple transparent conductive films disposed on the same side of the glass substrate. There is at least one slit structure formed on one of the transparent conductive films. Each slit structure corresponds to the color layer respectively. The one or multiple transparent conductive films can be used for shielding a liquid crystal layer of the display module.

Abstract: A fabricating method of a pixel structure is provided. A substrate has an array of pixel areas. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is formed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. The source and the drain is formed on two sides of the semiconductor layer. A passivation layer is formed on the substrate to cover the data line, the source and the drain. A pixel electrode is formed in each of the pixel areas, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. The common electrode wire is positioned only in a portion of the pixel area. A first capacitance storage electrode is disposed in each of the pixel areas and electrically connected between two adjacent common electrode wires. A gate insulation layer covers the scan line, the gate electrode, the common electrode wire and the first capacitance storage electrode. A semiconductor layer is disposed on the gate insulation layer above the gate electrode. The source and the drain are disposed on two sides of the semiconductor layer. A passivation layer is disposed on the substrate to cover the data line, the source and the drain. The passivation layer above the drain has a contact window. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: A pixel structure disposed on a substrate having an array of pixel areas is provided. A common electrode is disposed on the substrate to surround each of the pixel areas. A capacitance storage electrode is disposed on the common electrode. A first passivation layer covers the capacitance storage electrode and the common electrode. A gate insulation layer covers the scan line and the gate electrode. A semiconductor layer is disposed on the gate insulation layer. A data line, a source and a drain are disposed in each of the pixel areas and the source and the drain are disposed on two sides of the semiconductor layer. A second passivation layer has a contact window and covers the data line, the source, and the drain. A pixel electrode is disposed in each of the pixel areas and is electrically connected with the drain through the contact window.

Abstract: A fabricating method of a pixel structure is provided. First, a substrate with a plurality of pixel areas is provided. A common electrode is formed on the substrate to surround each pixel area. Then, a capacitance storage electrode is formed on the common electrode, and a first passivation layer is formed to cover the capacitance storage electrode and the common electrode. Following that, a scan line and a gate electrode are formed within each pixel area. Next, a gate insulation layer and a semiconductor layer are formed. A data line, a source, and a drain are formed within each pixel area. After that, a second passivation layer is formed on the substrate, and a contact window is formed in the second passivation layer above the drain. Moreover, a pixel electrode is formed within each pixel area, and the pixel electrode is electrically connected with the drain through the contact window.

Abstract: An active device array substrate at least including a substrate, a plurality of pixel units, a plurality of first signal lines, a first connecting wire, a plurality of first switching devices, and a plurality of second signal lines is provided. The pixel units are disposed within an active area. One ends of two neighboring first signal lines are respectively connected to a first test line and a second test line. The other ends of the two neighboring first signal lines are both connected to the first switching devices. Moreover, the first connecting wire is electrically connected to the first switching devices. One ends of two neighboring second signal lines are respectively connected to a third test line and a fourth test line.

Abstract: A pixel array substrate includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of active devices, a passivation layer, a common electrode, a dielectric layer, and a plurality of pixel electrodes. The substrate has a display area and a peripheral area. The scan lines and the data lines are intersected. The active devices are electrically connected to the scan lines and the data lines. The passivation layer covers the active devices. The common electrode is configured on the passivation layer and located in at least the display area. The dielectric layer covers the common electrode. The pixel electrodes are configured on the dielectric layer. Each of the pixel electrodes is electrically connected to one of the active devices. Each of the pixel electrodes has a plurality of slits. A portion of the common electrode under the slits is not shaded by the pixel electrodes.

Abstract: In a fabricating method of a pixel structure, a scan line and a gate electrode are formed in each pixel area of a substrate. A gate insulation layer is formed to cover the scan line and gate electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. A data line, source and drain are formed in each pixel area. A first passivation layer covers the data line, source and drain. A common line is formed on the first passivation layer and overlaps with at least a portion of the data line. A common electrode is formed on and electrically connected with the common line. A second passivation layer covers the common electrode and common line. A contact window is formed in the second passivation layer above the drain to expose the drain. A pixel electrode is electrically connected with the drain through the contact window.

Abstract: An active device array substrate, having at least a substrate, a first metal layer, an insulator layer, a second metal layer, a plurality of pixel electrodes and a plurality of active devices, is provided. The substrate has a display area and a narrow frame area. The first metal layer disposed on the substrate includes a plurality of first gate lines arranged laterally. The insulator layer is disposed on the first metal layer. The second metal layer disposed above an insulator layer includes a plurality of data lines and second gate lines arranged vertically. The first gate lines and the data lines divide the display area into a plurality of pixel areas. The second gate line disposed between the pixel areas is electrically connected to the first gate line. Each pixel electrode is electrically connected to the data line and the first gate line via each active array device.

Abstract: An inspecting circuit layout according to the present invention is provided. The inspecting circuit layout is adapted for inspecting panel units group by group, each of the panel units having a plurality of first and second signal lines. The inspecting circuit layout includes a multiplexer (MUX) and an inspecting pad. The MUX is electrically connected with at least one of the first or second signal lines of the panel units, and the inspecting pad is electrically connected to the MUX. The MUX is adapted for selectively connecting the inspecting pad with the first or second signal lines of a group of panel units.

Abstract: In a fabricating method of a pixel structure, a scan line and a gate electrode are formed in each pixel area of a substrate. A gate insulation layer is formed to cover the scan line and gate electrode. A semiconductor layer is formed on the gate insulation layer above the gate electrode. A data line, source and drain are formed in each pixel area. A first passivation layer covers the data line, source and drain. A common line is formed on the first passivation layer and overlaps with at least a portion of the data line. A common electrode is formed on and electrically connected with the common line. A second passivation layer covers the common electrode and common line. A contact window is formed in the second passivation layer above the drain to expose the drain. A pixel electrode is electrically connected with the drain through the contact window.