Patents by Inventor Meng-Chun Chen

Meng-Chun Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11981594
    Abstract: A method for preparing quartz glass with low content of hydroxyl and high purity, includes providing silica powders including hydroxyl groups. The silica powders are dehydroxylated, which includes drying the silica powders at a first temperature, heating the silica powders up to a second temperature and introducing a first oxidizing gas including halogen gas, thereby obtaining first dehydroxylated powders, and heating the first dehydroxylated powders up to a third temperature and introducing a second oxidizing gas including oxygen or ozone, thereby obtaining second dehydroxylated powders. The second dehydroxylated powders are heated up to a fourth temperature to obtain a vitrified body. The vitrified body is cooled to obtain the quartz glass with low content of hydroxyl and high purity. The quartz glass prepared by the above method has low content of hydroxyl and high purity. A quartz glass with low content of hydroxyl and high purity is also provided.
    Type: Grant
    Filed: December 9, 2020
    Date of Patent: May 14, 2024
    Assignees: ZHONGTIAN TECHNOLOGY ADVANCED MATERIALS CO., LTD., JIANGSU ZHONGTIAN TECHNOLOGY CO., LTD.
    Inventors: Ming-Ming Tang, Meng-Fei Wang, Yi-Gang Qian, Jun-Yi Ma, Xian-Gen Zhang, Yi-Chun Shen, Ya-Li Chen
  • Publication number: 20240150656
    Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, a fourth repeating unit, and a fifth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), the fourth repeating unit has a structure of Formula (IV), and the fifth repeating unit has a structure of Formula (V), a structure of Formula (VI), or a structure of Formula (VII) wherein A1, A2, A3, A4, X1, Z1, R1, R2, R3 and Q are as defined in the specification.
    Type: Application
    Filed: September 22, 2023
    Publication date: May 9, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin CHU, Jen-Chun CHIU, Po-Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
  • Publication number: 20240152321
    Abstract: A floating point pre-alignment structure for computing-in-memory applications includes a time domain exponent computing block and an input mantissa pre-align block. The time domain exponent computing block is configured to compute a plurality of original input exponents and a plurality of original weight exponents to generate a plurality of flags. Each of the flags is determined by adding one of the original input exponents and one of the original weight exponents. The input mantissa pre-align block is configured to receive a plurality of original input mantissas and shift the original input mantissas according to the flags to generate a plurality of weighted input mantissas, and sparsity of the weighted input mantissas is greater than sparsity of the original input mantissas. Each of the flags has a negative correlation with a sum of the one of the original input exponents and the one of the original weight exponents.
    Type: Application
    Filed: November 9, 2022
    Publication date: May 9, 2024
    Inventors: Meng-Fan CHANG, Ping-Chun WU, Jin-Sheng REN, Li-Yang HONG, Ho-Yu CHEN
  • Patent number: 11979980
    Abstract: A first and second patterned circuit layer are formed on a first surface and a second surface of a base material. A first adhesive layer is formed on the first patterned circuit layer. A portion of the first surface is exposed by the first patterned circuit layer. The metal reflection layer covers the first insulation layer and a reflectance thereof is greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer, and the first adhesive layer is disposed between the first patterned circuit layer and the first insulation layer. A transparent adhesive layer and a protection layer are formed on the metal reflection layer. The transparent adhesive layer is disposed between the metal reflection layer and the protection layer. The protection layer comprises a transparent polymer. The light transmittance is greater than or equal to 80%.
    Type: Grant
    Filed: August 19, 2021
    Date of Patent: May 7, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Publication number: 20240124706
    Abstract: A liquid crystal polymer, composition, liquid crystal polymer film, laminated material and method of forming liquid crystal polymer film are provided. The liquid crystal polymer includes a first repeating unit, a second repeating unit, a third repeating unit, and a fourth repeating unit. The first repeating unit has a structure of Formula (I), the second repeating unit has a structure of Formula (II), the third repeating unit has a structure of Formula (III), and the fourth repeating unit has a structure of Formula (IV), a structure of Formula (V) or a structure of Formula (VI) wherein A1, A2, A3, Z1, R1, R2, R3 and Q are as defined in the specification.
    Type: Application
    Filed: September 22, 2023
    Publication date: April 18, 2024
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Yu-Lin CHU, Jen-Chun CHIU, Po- Hsien HO, Yu-Min HAN, Meng-Hsin CHEN, Chih-Hsiang LIN
  • Patent number: 11937370
    Abstract: A base material is provided. A first patterned circuit layer and a second patterned circuit layer are formed on a first surface and a second surface of the base material. A first insulation layer and a metal reflection layer are provided on the first patterned circuit layer and a portion of the first surface exposed by the first patterned circuit layer, wherein the metal reflection layer covers the first insulation layer, and a reflectance of the metal reflection layer is substantially greater than or equal to 85%, there is no conductive material between the first patterned circuit layer and the metal reflection layer. A first ink layer is formed on the first insulation layer before the metal reflection layer is formed.
    Type: Grant
    Filed: September 1, 2021
    Date of Patent: March 19, 2024
    Assignee: UNIFLEX Technology Inc.
    Inventors: Cheng-I Tu, Ying-Hsing Chen, Meng-Huan Chia, Hsin-Ching Su, Yi-Chun Liu, Cheng-Chung Lai, Yuan-Chih Lee
  • Patent number: 11919997
    Abstract: A white photosensitive resin composition, a white spacer, a light conversion layer, and a light-emitting device are provided. The white photosensitive resin composition includes a polymerizable compound (A), an alkali-soluble resin (B), a photopolymerization initiator (C), a solvent (D), and a white pigment (E). The polymerizable compound (A) includes an ethylenically-unsaturated monomer (A-1) represented by formula (I-1) and a thiol compound (A-2) having two or more thiol groups in one molecule, wherein based on 100 mass % of the polymerizable compound (A), a total content of the ethylenically-unsaturated monomer (A-1) and the thiol compound (A-2) is 10 mass % to 98 mass %.
    Type: Grant
    Filed: May 25, 2021
    Date of Patent: March 5, 2024
    Assignee: eChem Solutions Corp.
    Inventors: Meng-Po Liu, Yu-Chun Chen
  • Patent number: 11850606
    Abstract: A particles capturing system includes a venturi filter device, a cyclone filter device, a plurality of first nozzles and air to flow through the system. The venturi filter device has an air intake portion, a neck portion and an air outlet portion. The cyclone filter device, disposed in the air outlet portion, has an entrance and an exit. The plurality of first nozzles, disposed inside the venturi filter device, have a height greater than that of the the neck portion. When the air flows, the air enters the venturi filter device via an air inlet of the air intake portion, then orderly passes through the neck portion and the plurality of first nozzles, then enters the cyclone filter device via the entrance, and finally leaves the cyclone filter device via the exit, such that particles in the flowing air can be captured.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 26, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Fu-Ching Tung, Hsuan-Fu Wang, Jwu-Sheng Hu, Yung-Jen Cheng, Hung-Cheng Yen, Meng-Chun Chen
  • Publication number: 20220071461
    Abstract: A particles capturing system includes a venturi filter device, a cyclone filter device, a plurality of first nozzles and air to flow through the system. The venturi filter device has an air intake portion, a neck portion and an air outlet portion. The cyclone filter device, disposed in the air outlet portion, has an entrance and an exit. The plurality of first nozzles, disposed inside the venturi filter device, have a height greater than that of the the neck portion. When the air flows, the air enters the venturi filter device via an air inlet of the air intake portion, then orderly passes through the neck portion and the plurality of first nozzles, then enters the cyclone filter device via the entrance, and finally leaves the cyclone filter device via the exit, such that particles in the flowing air can be captured.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 10, 2022
    Inventors: FU-CHING TUNG, HSUAN-FU WANG, JWU-SHENG HU, YUNG-JEN CHENG, HUNG-CHENG YEN, MENG-CHUN CHEN
  • Patent number: 10720440
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: July 21, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Publication number: 20190043877
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Application
    Filed: August 1, 2017
    Publication date: February 7, 2019
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Patent number: 10199385
    Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: February 5, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Wen-Peng Hsu, Chia-Wen Wang, Meng-Chun Chen, Chih-Hao Pan
  • Publication number: 20180211966
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Application
    Filed: March 21, 2018
    Publication date: July 26, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Patent number: 9966382
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Grant
    Filed: August 16, 2016
    Date of Patent: May 8, 2018
    Assignee: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Publication number: 20180053771
    Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.
    Type: Application
    Filed: August 16, 2016
    Publication date: February 22, 2018
    Applicant: United Microelectronics Corp.
    Inventors: Chia-Wen Wang, Hsiang-Chen Lee, Wen-Peng Hsu, Kuo-Lung Li, Meng-Chun Chen, Zi-Jun Liu, Ping-Chia Shih
  • Patent number: 9466497
    Abstract: The invention provides a method for fabricating a silicon-oxide-nitride-oxide-silicon (SONOS) non-volatile memory cell, comprising: (S1) forming a pad oxide pattern on a silicon substrate having a recess exposing a tunnel region of the silicon substrate; (S2) forming a bottom oxide layer, a nitride layer, a top oxide layer covering the recess and the pad oxide pattern to form a first ONO structure; (S3) forming a photoresist on the first ONO structure covering the recess and a peripheral region of the pad oxide pattern; (S4) removing a part of the first ONO structure exposed by the photoresist to form an U-shaped ONO structure; (S5) trimming the photoresist to exposed a part of the U-shaped ONO structure above the recess; (S6) removing the part of the U-shaped ONO structure; (S7) removing the photoresist; (S8) removing the pad oxide pattern and the top oxide layer; and (S9) forming a gate structure.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 11, 2016
    Assignee: UNITED MICROELECTRONICS CORPORATION
    Inventors: Kuo-Lung Li, Ping-Chia Shih, Hsiang-Chen Lee, Yu-Chun Chang, Chia-Wen Wang, Meng-Chun Chen, Chih-Yang Hsu
  • Patent number: 8254612
    Abstract: A sound system (30) for a portable electronic device (20) is provided. The sound system includes a sound generator (28), a sound processor (25), and a speaker subsystem (24). The sound generator is configured for generating sound recordings with single sound format. The sound processor electronically connects with the sound generator and is configured for receiving the sound recordings with single sound format transmitted from the sound processor. The sound processor is configured for processing the sound recordings with single sound format into sound recordings with 5.1 surround format. The speaker subsystem electronically connects with the sound processor and is configured for receiving the sound recordings with 5.1 surround format transmitted from the sound processor and playing the sound recordings with 5.1 surround format.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: August 28, 2012
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Meng-Chun Chen
  • Patent number: 8204257
    Abstract: A method for increasing ring tone volume is provided. The method includes steps of: reading an audio file which is set as a current ring tone; determining whether the ring tone is a MP3 audio file or a musical instrument digital interface (MIDI) audio file; adjusting frequencies by using an equalizer technique to increase volume of the ring tone if the ring tone is the MP3 audio file; adjusting a volume level of the ring tone to be the highest volume level, and adjusting timbre of the ring tone to increase the ring tone volume by simulating a musical score of the ring tone by using different instruments if the ring tone is the MIDI audio file. A related system is also provided.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: June 19, 2012
    Assignee: Chi Mei Communications Systems, Inc.
    Inventor: Meng-Chun Chen
  • Patent number: 8081767
    Abstract: A method for adjusting frequency response curve of a speaker comprises these steps: testing sensitivity of the speaker in at least two types of hardware conditions and recording corresponding frequency response curves; selecting a frequency response curve that comes closest to falling within a predetermined range for selected frequency ranges; and adjusting the selected frequency response curve with a filter.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: December 20, 2011
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Meng-Chun Chen
  • Patent number: 8059840
    Abstract: An exemplary method for locating sound sources is disclosed. The method includes the steps of: loading a sound source location program into a handheld device; activating the sound source location program; calculating a total voltage representing sound waves received by a microphone array via a waveform computation algorithm; calculating energy intensities of the total voltage according to the total voltage; and selecting a maximum energy intensity from the calculated energy intensities, and determining the location of the maximum energy intensity, the location of the maximum energy intensity is the location of the sound source. A related system is also disclosed.
    Type: Grant
    Filed: December 29, 2007
    Date of Patent: November 15, 2011
    Assignee: Chi Mei Communication Systems, Inc.
    Inventor: Meng-Chun Chen