Abstract: A semiconductor package includes a semiconductor die, a redistribution structure and connective terminals. The redistribution structure is disposed on the semiconductor die and includes a first metallization tier disposed in between a pair of dielectric layers. The first metallization tier includes routing conductive traces electrically connected to the semiconductor die and a shielding plate electrically insulated from the semiconductor die. The connective terminals include dummy connective terminals and active connective terminals. The dummy connective terminals are disposed on the redistribution structure and are electrically connected to the shielding plate. The active connective terminals are disposed on the redistribution structure and are electrically connected to the routing conductive traces. Vertical projections of the dummy connective terminals fall on the shielding plate.

Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.

Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.

Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.

Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.

Abstract: An electronic device including a voltage detection circuit, a control and protection circuit, at least one voltage converter, and a system-on-chip is provided. The voltage detection circuit detects a voltage source to output a voltage detection signal. The control and protection circuit, coupled to the voltage detection circuit, generates a system power enabling signal according to the voltage detection signal. The at least one voltage converter, coupled to the control and protection circuit, generates a system power signal according to the system power enabling signal. The system-on-chip, coupled to the at least one voltage converter, controls the electronic device when receiving the system power signal. In response to a power off signal generated from the system-on-chip, the control and protection circuit further isolates the voltage detection signal to avoid the transition of the voltage detection signal affecting a system shutdown procedure of the electronic device.

Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.

Abstract: Reliable, scalable, and tunable SERS substrates are developed for quantitative SERS measurements and the limit of detection (LOD) can be down to single molecule level. This is achieved by the precise control of SERS enhancement factor and detection hot zone using ligand-regulated nanoparticle superlattices film with a built-in internal standard. The establishment of quantitative SERS technique will open up many exciting opportunities for both fundamental and applied research areas.

Abstract: A heat dissipating module includes a heat sink and a number of latching assemblies. The heat sink includes a base and a number of positioning portions. A number of positioning holes is defined extending through the corresponding positioning portions and the base. Each latching assembly includes a latching member and a resilient member. The latching member includes a connecting pole, a head located at a first end portion of the connecting pole, and a latching portion located at a second end portion of the connecting pole. The resilient member is sleeved around the connecting pole. The latching portions of the latching members are extended through the corresponding positioning holes and engaged with a bottom surface of the base. Each resilient member is pressed between the corresponding head and the corresponding positioning portion.

Abstract: A packing member attached to non-coplanar outer surfaces of an electronic component includes a number of non-coplanar plates attached to the outer surfaces of the electronic component. A junction of every two adjacent plates defines a row of a plurality of through holes. A middle line of each row of through holes is aligned with a corresponding junction of two adjacent outer surfaces of the electronic component.

Abstract: An electronic device and a method for controlling fan speed of the electronic device include setting a speed range corresponding to a variety of pulse-width modulation (PWM) duty cycles of the fan, and setting a speed variation value of the fan. The method further includes reading the PWM duty cycle and detecting an actual speed of the fan, and adjusting the PWM duty cycle in the PWM duty cycle instruction according to the speed variation value.

Abstract: A ground mechanism for a heat sink is attached to a circuit board. The ground mechanism includes a first latching member, a second latching member, a conductive member, and an elastic member. The first latching member and a second latching member latch the heat sink on the circuit board. The conductive member is formed on the circuit board. The elastic member is sandwiched between the first latching member and the heat sink. The elastic member electrically connects the first latching member to the heat sink, and the second latching member electrically connect the first latching member to the conductive member to conduct electromagnetic charges from the heat sink to a grounding pin of the circuit board.

Abstract: An apparatus for fixing a heat sink having a bottom plate includes a circuit board, two fasteners, and two blocks. The circuit board defines two through holes. The fasteners respectively extend through the bottom plate of the heat sink for fixing the heat sink to the circuit board. Each of the fasteners includes two spaced feet to extend through a corresponding one of the through holes and engage with a bottom of the circuit board. Each of the blocks is inserted into a space between the feet of a corresponding one of the fasteners after the feet extend through the corresponding through hole, to prevent the feet from deforming and disengaging from the circuit board.

Abstract: One embodiment of the present invention provides a method for forming a nanoparticle film, which comprises the steps of: preparing a nanoparticle solution, which comprises a solvent and supersaturated nanoparticles with surface ligand molecules; and dip coating a substrate to the nanoparticle solutions to form a first monolayer of the nanoparticles on the substrate, the first monolayer and repeatedly formed monolayers on top of the first monolayer constructing the nanoparticle film. Another embodiment of the present invention provides a nanoparticle film, comprising a first monolayer consisted of a two-dimensional nanoparticles array that are near-field coupled with each other to have tunable plasmonic properties by changing the number of stacked monolayers.

Abstract: A computer system includes an enclosure having an air intake, a heat sink and an electronic element. The heat sink includes a first heat dissipating portion, a second heat dissipating portion, and a third heat dissipating portion interconnecting the first and second heat dissipating portions. Each of the first heat dissipating portion, second heat dissipating portion, and third heat dissipating portion includes a number of fins and passages formed between each two adjacent fins. The passages of the first heat dissipating portion face toward the air intake. A space is maintained between the first heat dissipating portion and the second heat dissipating portion, and the electronic element is mounted in the space.

Abstract: A fan speed control system includes a fan, a hardware device, and a basic input/output system (BIOS) module. The BIOS module includes a memory unit, an edit unit, a searching unit, and a control unit. The memory unit stores a matching table of different hardware device numbers and corresponding fan speed control curves. The edit unit is operable to edit the matching table. The searching unit is operable to read the matching table and search which fan speed control curve matches with the hardware device number of the hardware device. The control unit is operable to select the matched fan speed control curve to control the fan speed of the fan.

Abstract: An exemplary computer enclosure includes a chassis, a mounting frame, two air-guiding members, and a fan. The chassis includes a first side panel, a second side panel, and a ventilation area defining ventilation through holes. The mounting frame is fixed to the chassis and faces the ventilation through holes. The mounting frame is configured for receiving electronic components. The two air-guiding members respectively connect two opposite sides of the mounting frame to the chassis. The two air-guiding members incline relative to the mounting frame and the chassis to form an air passage. The fan is configured for exhausting air passing through the ventilation through holes and the mounting frame. The two air-guiding members and the first and second side panels cooperatively surround the ventilation area to allow the air to enter the chassis from the ventilation area and allow all of the air to pass through the mounting frame.

Abstract: A heat sink includes a substrate, a first heat dissipation body, and a second heat dissipation. The first heat dissipation body includes a first base plate attached to the substrate, and a number of first cooling fins extending from the first base plate. The second heat dissipation body includes a second base plate attached to tops of first cooling fins and a number of second cooling fins extending from the second base plate.