Patents by Inventor Meng-Hsien Lin

Meng-Hsien Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250048658
    Abstract: In some embodiments, the present disclosure relates to an integrated device, including a substrate; an interconnect structure disposed over the substrate, the interconnect structure including an dielectric; a first bottom electrode structure disposed in the dielectric, the first bottom electrode structure having a first width as measured between outer sidewalls of the first bottom electrode structure and a first depth as measured from an upper surface of the dielectric; and a second bottom electrode structure disposed in the dielectric and spaced apart from the first bottom electrode structure, the second bottom electrode structure having a second width as measured between outer sidewalls of the second bottom electrode structure and a second depth as measured from the upper surface of the dielectric; where the first width is greater than the second width and the first depth is greater than the second depth.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 6, 2025
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Wei-Chih Weng, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung
  • Patent number: 12204163
    Abstract: An optical system affixed to an electronic apparatus is provided, including a first optical module, a second optical module, and a third optical module. The first optical module is configured to adjust the moving direction of a first light from a first moving direction to a second moving direction, wherein the first moving direction is not parallel to the second moving direction. The second optical module is configured to receive the first light moving in the second moving direction. The first light reaches the third optical module via the first optical module and the second optical module in sequence. The third optical module includes a first photoelectric converter configured to transform the first light into a first image signal.
    Type: Grant
    Filed: February 5, 2024
    Date of Patent: January 21, 2025
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Chih-Wei Weng, Chia-Che Wu, Chien-Yu Kao, Hsiao-Hsin Hu, He-Ling Chang, Chao-Hsi Wang, Chen-Hsien Fan, Che-Wei Chang, Mao-Gen Jian, Sung-Mao Tsai, Wei-Jhe Shen, Yung-Ping Yang, Sin-Hong Lin, Tzu-Yu Chang, Sin-Jhong Song, Shang-Yu Hsu, Meng-Ting Lin, Shih-Wei Hung, Yu-Huai Liao, Mao-Kuo Hsu, Hsueh-Ju Lu, Ching-Chieh Huang, Chih-Wen Chiang, Yu-Chiao Lo, Ying-Jen Wang, Shu-Shan Chen, Che-Hsiang Chiu
  • Publication number: 20250022912
    Abstract: An embodiment high-density capacitor includes a bottom electrode having a plurality of non-concentric cylindrical portions, a top electrode including a plurality of vertical portions and a surrounding portion, and a dielectric layer separating the top electrode from the bottom electrode. Each of the plurality of non-concentric cylindrical portions includes an inner shell and an outer shell and each of the plurality of vertical portions is vertically surrounded by the inner shell of a respective cylindrical portion of the bottom electrode. The surrounding portion of the top electrode respectively vertically surrounds each of the plurality of non-concentric cylindrical portions of the bottom electrode such that adjacent non-concentric cylindrical portions of the bottom electrode are separated from one another by the surrounding portion of the top electrode. At least some of the plurality of non-concentric cylindrical portions of the bottom electrode include a spatial distribution having a hexagonal symmetry.
    Type: Application
    Filed: July 14, 2023
    Publication date: January 16, 2025
    Inventors: Meng-Hsien Lin, Dun-Nian Yaung, Jen-Cheng Liu, Hsing-Chih Lin, Ko Chun Liu
  • Patent number: 12176664
    Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: December 24, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Wei-Kai Hsiao, Meng-Hsien Lin
  • Patent number: 12154939
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Grant
    Filed: July 28, 2023
    Date of Patent: November 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240387613
    Abstract: The present disclosure, in some embodiments, relates to a capacitor structure. The capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A lower electrode is arranged along sidewalls and an upper surface of the lower dielectric structure, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is arranged along outermost sidewalls of the upper electrode. The spacer includes a first upper surface arranged along a first side of the upper electrode and a second upper surface arranged along an opposing second side of the upper electrode. The first upper surface has a different width than the second upper surface.
    Type: Application
    Filed: July 25, 2024
    Publication date: November 21, 2024
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20240355740
    Abstract: A method includes forming a dielectric layer over a conductive feature, and etching the dielectric layer to form an opening. The conductive feature is exposed through the opening. The method further includes forming a tungsten liner in the opening, wherein the tungsten liner contacts sidewalls of the dielectric layer, depositing a tungsten layer to fill the opening, and planarizing the tungsten layer. Portions of the tungsten layer and the tungsten liner in the opening form a contact plug.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 24, 2024
    Inventors: Feng-Yu Chang, Sheng-Hsuan Lin, Shu-Lan Chang, Kai-Yi Chu, Meng-Hsien Lin, Pei-Hsuan Lee, Pei Shan Chang, Chih-Chien Chi, Chun-I Tsai, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai, Syun-Ming Jang, Wei-Jen Lo
  • Publication number: 20240096784
    Abstract: Some embodiments of the present disclosure relate to an integrated chip including an extended via that spans a combined height of a wire and a via and that has a smaller footprint than the wire. The extended via may replace a wire and an adjoining via at locations where the sizing and the spacing of the wire are reaching lower limits. Because the extended via has a smaller footprint than the wire, replacing the wire and the adjoining via with the extended via relaxes spacing and allows the size of the pixel to be further reduced. The extended via finds application for capacitor arrays used for pixel circuits.
    Type: Application
    Filed: January 3, 2023
    Publication date: March 21, 2024
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ming-Tsong Wang, Min-Feng Kao, Kuan-Hua Lin, Jen-Cheng Liu, Dun-Nian Yaung, Ko Chun Liu
  • Publication number: 20230411277
    Abstract: Capacitors and interconnect structures that couple transistors to one another include parallel stacked metal lines separated by dielectric layers. When capacitors and interconnect structures are combined, each top metal capacitor plate can be coupled to the nearest upper metal line by a through-via, while each bottom metal capacitor plate can be coupled directly to the nearest lower metal line without a via. When a back end of line (BEOL) cell includes multiple capacitors, and design rules require shrinking the cell dimensions, substituting an alternative design that has fewer through-vias can facilitate compaction of the BEOL cell. Similarly, placing capacitors in close proximity so that they can share through-vias can allow even further compaction.
    Type: Application
    Filed: June 17, 2022
    Publication date: December 21, 2023
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsien Lin, Hsing-Chih Lin, Ke Chun Liu, Min-Feng Kao, Kuan-Hua Lin
  • Publication number: 20230369389
    Abstract: The present disclosure, in some embodiments, relates to a metal-insulator-metal (MIM) capacitor structure. The MIM capacitor structure includes one or more lower interconnects disposed within a lower dielectric structure over a substrate. A first dielectric layer is over the lower dielectric structure and includes sidewalls defining a plurality of openings extending through the first dielectric layer. A lower electrode is arranged along the sidewalls and over an upper surface of the first dielectric layer, a capacitor dielectric is arranged along sidewalls and an upper surface of the lower electrode, and an upper electrode is arranged along sidewalls and an upper surface of the capacitor dielectric. A spacer is along opposing outermost sidewalls of the upper electrode. The spacer has an outermost surface extending from a lowermost surface of the spacer to a top of the spacer. The outermost surface is substantially aligned with an outermost sidewall of the lower electrode.
    Type: Application
    Filed: July 28, 2023
    Publication date: November 16, 2023
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Patent number: 11769791
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Grant
    Filed: May 5, 2021
    Date of Patent: September 26, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20230291159
    Abstract: A power connector module is provided, including a housing, an electrical connector unit disposed in a first space of the housing, and a socket unit disposed in a second space of the housing. The glue is received in the first space, and a gate plate is disposed on a diaphragm of the housing to prevent the glue from flowing into the second space.
    Type: Application
    Filed: June 27, 2022
    Publication date: September 14, 2023
    Inventors: Wei-Kai HSIAO, Meng-Hsien LIN
  • Patent number: 11742748
    Abstract: An electronic device including a voltage detection circuit, a control and protection circuit, at least one voltage converter, and a system-on-chip is provided. The voltage detection circuit detects a voltage source to output a voltage detection signal. The control and protection circuit, coupled to the voltage detection circuit, generates a system power enabling signal according to the voltage detection signal. The at least one voltage converter, coupled to the control and protection circuit, generates a system power signal according to the system power enabling signal. The system-on-chip, coupled to the at least one voltage converter, controls the electronic device when receiving the system power signal. In response to a power off signal generated from the system-on-chip, the control and protection circuit further isolates the voltage detection signal to avoid the transition of the voltage detection signal affecting a system shutdown procedure of the electronic device.
    Type: Grant
    Filed: May 31, 2022
    Date of Patent: August 29, 2023
    Assignee: Qisda Corporation
    Inventor: Meng-Hsien Lin
  • Publication number: 20220238636
    Abstract: The present disclosure, in some embodiments, relates to a method of forming a capacitor structure. The method includes forming a capacitor dielectric layer over a lower electrode layer, and forming an upper electrode layer over the capacitor dielectric layer. The upper electrode layer is etched to define an upper electrode and to expose a part of the capacitor dielectric layer. A spacer structure is formed over horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and also along sidewalls of the upper electrode. The spacer structure is etched to remove the spacer structure from over the horizontally extending surfaces of the upper electrode layer and the capacitor dielectric layer and to define a spacer. The capacitor dielectric layer and the lower electrode layer are etched according to the spacer to define a capacitor dielectric and a lower electrode.
    Type: Application
    Filed: May 5, 2021
    Publication date: July 28, 2022
    Inventors: Ching-Sheng Chu, Dun-Nian Yaung, Yu-Cheng Tsai, Meng-Hsien Lin, Ching-Chung Su, Jen-Cheng Liu, Wen-De Wang, Guan-Hua Chen
  • Publication number: 20170261434
    Abstract: Reliable, scalable, and tunable SERS substrates are developed for quantitative SERS measurements and the limit of detection (LOD) can be down to single molecule level. This is achieved by the precise control of SERS enhancement factor and detection hot zone using ligand-regulated nanoparticle superlattices film with a built-in internal standard. The establishment of quantitative SERS technique will open up many exciting opportunities for both fundamental and applied research areas.
    Type: Application
    Filed: March 9, 2016
    Publication date: September 14, 2017
    Inventors: Shang-Jr Gwo, Hung-Ying Chen, Meng-Hsien Lin
  • Publication number: 20150144317
    Abstract: A heat dissipating module includes a heat sink and a number of latching assemblies. The heat sink includes a base and a number of positioning portions. A number of positioning holes is defined extending through the corresponding positioning portions and the base. Each latching assembly includes a latching member and a resilient member. The latching member includes a connecting pole, a head located at a first end portion of the connecting pole, and a latching portion located at a second end portion of the connecting pole. The resilient member is sleeved around the connecting pole. The latching portions of the latching members are extended through the corresponding positioning holes and engaged with a bottom surface of the base. Each resilient member is pressed between the corresponding head and the corresponding positioning portion.
    Type: Application
    Filed: September 4, 2014
    Publication date: May 28, 2015
    Inventor: MENG-HSIEN LIN
  • Publication number: 20150016031
    Abstract: A packing member attached to non-coplanar outer surfaces of an electronic component includes a number of non-coplanar plates attached to the outer surfaces of the electronic component. A junction of every two adjacent plates defines a row of a plurality of through holes. A middle line of each row of through holes is aligned with a corresponding junction of two adjacent outer surfaces of the electronic component.
    Type: Application
    Filed: July 25, 2013
    Publication date: January 15, 2015
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: CHIH-TA HUANG, MENG-HSIEN LIN, YAO-TING CHANG
  • Patent number: 8606429
    Abstract: An electronic device and a method for controlling fan speed of the electronic device include setting a speed range corresponding to a variety of pulse-width modulation (PWM) duty cycles of the fan, and setting a speed variation value of the fan. The method further includes reading the PWM duty cycle and detecting an actual speed of the fan, and adjusting the PWM duty cycle in the PWM duty cycle instruction according to the speed variation value.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: December 10, 2013
    Assignee: Hon Hai Precision Industry Co., Ltd.
    Inventors: Meng-Hsien Lin, Yao-Ting Chang
  • Publication number: 20130208427
    Abstract: A ground mechanism for a heat sink is attached to a circuit board. The ground mechanism includes a first latching member, a second latching member, a conductive member, and an elastic member. The first latching member and a second latching member latch the heat sink on the circuit board. The conductive member is formed on the circuit board. The elastic member is sandwiched between the first latching member and the heat sink. The elastic member electrically connects the first latching member to the heat sink, and the second latching member electrically connect the first latching member to the conductive member to conduct electromagnetic charges from the heat sink to a grounding pin of the circuit board.
    Type: Application
    Filed: April 27, 2012
    Publication date: August 15, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: MENG-HSIEN LIN, YAO-TING CHANG
  • Publication number: 20130126214
    Abstract: An apparatus for fixing a heat sink having a bottom plate includes a circuit board, two fasteners, and two blocks. The circuit board defines two through holes. The fasteners respectively extend through the bottom plate of the heat sink for fixing the heat sink to the circuit board. Each of the fasteners includes two spaced feet to extend through a corresponding one of the through holes and engage with a bottom of the circuit board. Each of the blocks is inserted into a space between the feet of a corresponding one of the fasteners after the feet extend through the corresponding through hole, to prevent the feet from deforming and disengaging from the circuit board.
    Type: Application
    Filed: December 24, 2011
    Publication date: May 23, 2013
    Applicant: HON HAI PRECISION INDUSTRY CO., LTD.
    Inventors: MENG-HSIEN LIN, YAO-TING CHANG