Patents by Inventor Meng-Hsuan Hsiao

Meng-Hsuan Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210226005
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Application
    Filed: April 6, 2021
    Publication date: July 22, 2021
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Publication number: 20210226042
    Abstract: A method of manufacturing a semiconductor device includes forming a stacked structure of first semiconductor layers and second semiconductor layers alternately stacked in a first direction over a substrate. A thickness of the first semiconductor layers as formed increases in each first semiconductor layer spaced further apart from the substrate in the first direction. The stacked structure is patterned into a fin structure extending along a second direction substantially perpendicular to the first direction. A portion of the first semiconductor layers between adjacent second semiconductor layers is removed, and a gate structure is formed extending in a third direction over a first portion of the first semiconductor layers so that the gate structure wraps around the first semiconductor layers. The third direction is substantially perpendicular to both the first direction and the second direction.
    Type: Application
    Filed: January 17, 2020
    Publication date: July 22, 2021
    Inventors: Meng-Hsuan HSIAO, Tung Ying LEE, Wei-Sheng YUN, Jin CAI
  • Patent number: 11043556
    Abstract: The disclosed technique forms epitaxy layers locally within a trench having angled recesses stacked in the sidewall of the trench. The sizes of the recesses are controlled to control the thickness of the epitaxy layers to be formed within the trench. The recesses are covered by cap layers and exposed one by one sequentially beginning from the lowest recess. The epitaxy layers are formed one by one within the trench with the facet edge portion thereof aligned into the respective recess, which is the recess sequentially exposed for the epitaxy layer.
    Type: Grant
    Filed: May 7, 2019
    Date of Patent: June 22, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ling-Yen Yeh, Meng-Hsuan Hsiao, Yuan-Chen Sun
  • Patent number: 11038036
    Abstract: The current disclosure describes techniques for forming gate-all-around (“GAA”) devices from stacks of separately formed nanowire semiconductor strips. The separately formed nanowire semiconductor strips are tailored for the respective GAA devices. A trench is formed in a first stack of epitaxy layers to define a space for forming a second stack of epitaxy layers. The trench bottom is modified to have determined or known parameters in the shapes or crystalline facet orientations. The known parameters of the trench bottom are used to select suitable processes to fill the trench bottom with a relatively flat base surface.
    Type: Grant
    Filed: August 8, 2019
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tung Ying Lee, Kai-Tai Chang, Meng-Hsuan Hsiao
  • Publication number: 20210151434
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate and a semiconductor layer formed over a substrate. The semiconductor device further includes an isolation region covering the semiconductor layer and nanostructures formed over the semiconductor layer. The semiconductor layer further includes a gate stack wrapping around the nanostructures. In addition, the isolation region is interposed between the semiconductor layer and the gate stack.
    Type: Application
    Filed: January 4, 2021
    Publication date: May 20, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Patent number: 11007005
    Abstract: In a method of forming a FinFET, a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is recessed so that a remaining layer of the first sacrificial layer is formed on the isolation insulating layer and an upper portion of the source/drain structure is exposed. A second sacrificial layer is formed on the remaining layer and the exposed source/drain structure. The second sacrificial layer and the remaining layer are patterned, thereby forming an opening. A dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first and second sacrificial layers are removed to form a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: May 24, 2018
    Date of Patent: May 18, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Ziwei Fang, Yee-Chia Yeo, Meng-Hsuan Hsiao
  • Publication number: 20210074812
    Abstract: A semiconductor device includes a fin structure, a two-dimensional (2D) material channel layer, a ferroelectric layer, and a metal layer. The fin structure extends from a substrate. The 2D material channel layer wraps around at least three sides of the fin structure. The ferroelectric layer wraps around at least three sides of the 2D material channel layer. The metal layer wraps around at least three sides of the ferroelectric layer.
    Type: Application
    Filed: October 30, 2020
    Publication date: March 11, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh LU, Meng-Hsuan HSIAO, Tung-Ying LEE, Ling-Yen YEH, Chih-Sheng CHANG, Carlos H. DIAZ
  • Publication number: 20210050457
    Abstract: A method for forming a gate-all-around structure is provided. The method includes forming a plurality of a first type of semiconductor layers and a plurality of a second type of semiconductor layers alternately stacked over a fin. The first type of semiconductor layers includes a first semiconductor layer and a second semiconductor layer, and the first semiconductor layer has a thickness greater than that of the second semiconductor layer. The method also includes removing the second type of semiconductor layers. In addition, the method includes forming a gate to wrap around the first type of semiconductor layers.
    Type: Application
    Filed: November 2, 2020
    Publication date: February 18, 2021
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Meng-Hsuan HSIAO, Wei-Sheng YUN, Winnie Victoria Wei-Ning CHEN, Tung Ying LEE, Ling-Yen YEH
  • Patent number: 10886270
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer. The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: January 5, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Patent number: 10886268
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. A mask pattern is formed over the sacrificial layer. The sacrificial layer and the source/drain structure are patterned by using the mask pattern as an etching mask, thereby forming openings adjacent to the patterned sacrificial layer and source/drain structure. A dielectric layer is formed in the openings. After the dielectric layer is formed, the patterned sacrificial layer is removed to form a contact opening over the patterned source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: February 10, 2017
    Date of Patent: January 5, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Tsung-Lin Lee, Yee-Chia Yeo, Meng-Hsuan Hsiao
  • Patent number: 10872955
    Abstract: A semiconductor device includes a fin structure extending along a first direction, a channel layer wrapping around a top surface and opposite sidewalls of the fin structure, a gate stack extending across the channel layer along a second direction perpendicular to the first direction, and a spacer on a top surface of the channel layer and a sidewall of the gate stack when viewed in a cross section taken along the first direction. The channel layer includes a two-dimensional material. The gate stack includes a ferroelectric layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 22, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Meng-Hsuan Hsiao, Tung-Ying Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10867841
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Meng-Hsuan Hsiao, Yee-Chia Yeo, Tung Ying Lee, Chih Chieh Yeh
  • Patent number: 10868009
    Abstract: A method for forming a semiconductor device is provided. The method includes forming a first recess in a substrate. The method includes forming a first semiconductor layer into the first recess. The first semiconductor layer and the substrate are made of different materials, and a first top surface of the first semiconductor layer is lower than a second top surface of the substrate. The method includes forming a second semiconductor layer over the first top surface and the second top surface, wherein a third top surface of the second semiconductor layer over the first top surface is substantially level with the second top surface of the substrate, and the second semiconductor layer and the substrate are made of different materials. The method includes forming a third semiconductor layer over the second semiconductor layer. The third semiconductor layer and the second semiconductor layer are made of different materials.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning Chen, Meng-Hsuan Hsiao, Tung-Ying Lee, Pang-Yen Tsai, Yasutoshi Okuno
  • Publication number: 20200358873
    Abstract: In a method for forming an integrated semiconductor device, a first transistor over is formed on a substrate; an inter-layer dielectric (ILD) layer is deposited over the first transistor; a gate conductive layer is deposited over the ILD layer; a gate dielectric layer is deposited over the gate conductive layer; the gate dielectric layer and the gate conductive layer are etched to form a gate stack; and a 2D material layer that has a first portion extending along a top surface and sidewalls of the gate stack and a second portion extending along a top surface of the ILD layer.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Cheng-Yi PENG, Chun-Chieh LU, Meng-Hsuan HSIAO, Ling-Yen YEH, Carlos H. DIAZ, Tung-Ying LEE
  • Publication number: 20200357684
    Abstract: In a method of forming a semiconductor device including a fin field effect transistor (FinFET), a first sacrificial layer is formed over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of opening and at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, a dielectric layer is formed in the opening. After the dielectric layer is formed, the patterned first sacrificial layer is removed, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening.
    Type: Application
    Filed: July 27, 2020
    Publication date: November 12, 2020
    Inventors: Meng-Hsuan HSIAO, Yee-Chia YEO, Tung Ying LEE, Chih Chieh YEH
  • Patent number: 10825899
    Abstract: A method of fabricating a semiconductor device includes forming a fin structure on a substrate, forming a channel layer on a sidewall and a top surface of the fin structure, and forming a gate stack over the channel layer. The channel layer includes a two-dimensional (2D) material. The gate stack includes a ferroelectric layer.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: November 3, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chun-Chieh Lu, Meng-Hsuan Hsiao, Tung-Ying Lee, Ling-Yen Yeh, Chih-Sheng Chang, Carlos H. Diaz
  • Patent number: 10825933
    Abstract: Present disclosure provides gate-all-around structure including a semiconductor fin having a top surface, a first nanowire over the top surface, a first space between the top surface and the first nanowire, an Nth nanowire and an (N+1)th nanowire over the first nanowire, and a second space between the Nth nanowire and the (N+1)th nanowire. The first space is greater than the second space. Present disclosure also provides a method for manufacturing the gate-all-around structure described herein.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: November 3, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Meng-Hsuan Hsiao, Wei-Sheng Yun, Winnie Victoria Wei-Ning Chen, Tung Ying Lee, Ling-Yen Yeh
  • Publication number: 20200321336
    Abstract: A method for forming a semiconductor device is provided. The method includes removing a first portion of a substrate to form a recess in the substrate. The method includes forming an epitaxy layer in the recess. The epitaxy layer and the substrate are made of different semiconductor materials. The method includes forming a stacked structure of a plurality of first semiconductor layers and a plurality of second semiconductor layers alternately stacked over the substrate and the epitaxy layer. The method includes removing a second portion of the stacked structure and a third portion of the epitaxy layer to form trenches passing through the stacked structure and extending into the epitaxy layer, The stacked structure is divided into a first fin element and a second fin element by the trenches, and the first fin element and the second fin element are over the substrate and the epitaxy layer respectively.
    Type: Application
    Filed: June 24, 2020
    Publication date: October 8, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Winnie Victoria Wei-Ning CHEN, Meng-Hsuan HSIAO, Tung-Ying LEE, Pang-Yen TSAI, Yasutoshi OKUNO
  • Publication number: 20200303260
    Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET) includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer including Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, and 0.01?x?0.1, and 0.01?y?0.1.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO
  • Publication number: 20200303259
    Abstract: A method of forming a semiconductor device including a fin field effect transistor (FinFET), the method includes forming a first sacrificial layer over a source/drain structure of a FinFET structure and an isolation insulating layer. The first sacrificial layer is patterned, thereby forming an opening. A first liner layer is formed on the isolation insulating layer in a bottom of the opening and on at least side faces of the patterned first sacrificial layer. After the first liner layer is formed, forming a dielectric layer in the opening. After the dielectric layer is formed, removing the patterned first sacrificial layer, thereby forming a contact opening over the source/drain structure. A conductive layer is formed in the contact opening. The FinFET is an n-type FET, and the source/drain structure includes an epitaxial layer made of Si1-y-a-bGeaSnbM2y, wherein 0<a, 0<b, 0.01?(a+b)?0.1, 0.01?y?0.1, and M2 is P or As.
    Type: Application
    Filed: June 9, 2020
    Publication date: September 24, 2020
    Inventors: Yasutoshi OKUNO, Cheng-Yi PENG, Ziwei FANG, I-Ming CHANG, Akira MINEJI, Yu-Ming LIN, Meng-Hsuan HSIAO