Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch, a variable resistance circuit, and a judgment circuit. A first terminal of the control switch is coupled to the control pin. The variable resistance circuit is coupled between a second terminal of the control switch and a reference low voltage. The judgment circuit controls the variable resistance circuit to provide a detection resistance value with a minimum value, and turns on the control switch to obtain a sensing voltage value. When the detection resistance value has a maximum value and the sensing voltage value is lower than a reference voltage value, the judgment circuit provides a notification signal.

Abstract: A controller for controlling a blocking switch of a power converter is provided. The controller includes a control pin and a sensing circuit. The control pin is coupled to a control terminal of the blocking switch and an output terminal of the blocking switch. The sensing circuit includes a control switch and a judgment circuit. A first terminal of the control switch is coupled to the control pin. A second terminal of the control switch is coupled to a reference low voltage. The judgment circuit turns on the control switch during a period when the blocking switch is turned off to obtain a sensing current value of a current flowing through the control switch. When the sensing current value is lower than a reference current value, the judgment circuit provides a notification signal for allowing the blocking switch to be turned on.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

Abstract: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.

Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

Abstract: A memory device includes: a resistive switching layer, a conductive pillar, a barrier layer, a word line, a plurality of resistive layers, and a plurality of bit lines. The resistive switching layer is shaped as a cup and has an inner surface to define an opening. The conductive pillar is disposed in the opening. The barrier layer is disposed between the resistive switching layer and the conductive pillar. The word line is electrically connected to the conductive pillar. The resistive layers are respectively distributed on an outer surface of the resistive switching layer. The bit lines are electrically connected to the resistive layers, respectively.

Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.

Abstract: A RRAM and its manufacturing method are provided. The RRAM includes an interlayer dielectric layer, a first bottom contact structure, and a second bottom contact structure formed on a substrate. A first memory cell is formed on the first bottom contact structure. The first memory cell includes a first bottom electrode layer which includes a first conductive region. A pattern in which the first conductive region is vertically projected on the first bottom contact structure is a first projection pattern. A second memory cell is formed on the second bottom contact structure. The second memory cell includes a second bottom electrode layer which includes a second conductive region. A pattern in which the second conductive region is vertically projected on the second bottom contact structure is a second projection pattern. The second projection pattern is different from the first projection pattern.

Abstract: An RRAM structure and its manufacturing method are provided. The RRAM structure includes a bottom electrode layer, a resistance switching layer, and an implantation control layer sequentially formed on a substrate. The resistance switching layer includes a conductive filament confined region and an outer region surrounding the conductive filament confined region. The RRAM structure includes a protective layer and a top electrode layer. The protective layer conformally covers the bottom electrode layer, the resistance switching layer, and the implantation control layer and has a first opening. The top electrode layer is located on the implantation control layer, and a portion of the top electrode layer is filled into the first opening. The position of the top electrode layer corresponds to that of the conductive filament confined region, and the top surface of the top electrode layer is higher than that of the protective layer.

Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

Abstract: A resistive random access memory (RRAM) is provided. The RRAM includes a lower electrode, an upper electrode, a first variable resistance layer and a second variable resistance layer. The lower electrode is disposed on a substrate, and is a single electrode or a pair of electrodes electrically connected to each other. The upper electrode is disposed on the lower electrode, and overlaps the lower electrode. The first variable resistance layer and the second variable resistance layer are disposed on the substrate. At least a portion of the first variable resistance layer is disposed between the lower electrode and the upper electrode, and at least a portion of the second variable resistance layer is disposed between the lower electrode and the upper electrode and connected to the first variable resistance layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

Abstract: A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.

Abstract: A key generator including a first access circuit, a first calculating circuit and a first certification circuit is provided. The first access circuit writes first predetermined data to a first resistive memory cell during a write period and reads a first current passing through the first resistive memory cell after a randomization process. The first calculating circuit calculates the first current to generate a first calculation result. The first certification circuit generates a first password according to the first calculation result.

Abstract: A memory storage apparatus including a memory cell array and a memory control circuit is provided. The memory cell array includes a plurality of memory cells. The memory cell array is configured to store data. The memory control circuit is coupled to the memory cell array. The memory control circuit is configured to apply one of a set signal and a reset signal to a target memory cell among the memory cells to generate a read current. The memory control circuit receives a read current of the target memory cell. The memory control circuit compares the read current with a reference current. The memory control circuit determines whether the target memory cell is failed according to a comparison result. In addition, a method for testing a memory storage apparatus is also provided.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.

Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.

Abstract: The invention provides a memory device and a manufacturing method thereof. The memory device includes a substrate, a capacitor, a protection device, a first metal interconnect, and a second metal interconnect. The capacitor is located on the substrate of a first region. The protection device is located in the substrate of a second region. The capacitor includes a plurality of bottom electrodes, a top electrode, and a capacitor dielectric layer. The top electrode has a first portion and a second portion, wherein the second portion is extended to the second region. The capacitor dielectric layer is located between the bottom electrodes and the top electrode. The first metal interconnect is located between the capacitor and the substrate. The second metal interconnect is located between the second portion of the top electrode and the protection device. The top electrode is electrically connected to the protection device through the second metal interconnect.