Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract: The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer.

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract: The present invention relates to a semiconductor structure and a method for making the same. The method includes the following steps: (a) providing a first wafer and a second wafer; (b) disposing the first wafer on the second wafer; (c) removing part of the first wafer, so as to form a groove; (d) forming a through via in the groove; and (e) forming at least one electrical connecting element on the first wafer. Therefore, the wafers are penetrated and electrically connected by forming only one conductive via, which leads to a simplified process and a low manufacturing cost.

Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, including a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying the position and direction on the backside surface. Thus, the redistribution layer (RBL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

Abstract: The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

Abstract: The present invention relates to a semiconductor element having a conductive via and a method for making the same and a package having a semiconductor element with a conductive via. The semiconductor element includes a silicon chip and at least one conductive via. The silicon chip includes a silicon substrate and an active circuit layer. The active circuit layer is disposed on a second surface of the silicon substrate, and has at least one metal layer. The conductive via penetrates the silicon substrate, and includes a conductive metal. The conductive metal electrically connects to the metal layer of the active circuit layer, and a surface of the conductive metal is exposed to the outside of a first surface of the silicon substrate. Therefore, a chip is able to be directly stacked on the semiconductor element without forming a passivation layer and a redistribution layer on the first surface of the silicon substrate, and the process is simplified and the manufacturing cost is decreased.

Abstract: A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

Abstract: A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.

Abstract: The present invention relates to a method for making a stackable package. The method includes the following steps: (a) providing a first carrier; (b) disposing at least one chip on the first carrier; (c) forming a molding compound so as to encapsulate the chip; (d) removing the first carrier; (e) forming a first redistribution layer and at least one first bump; (f) providing a second carrier; (g) disposing on the second carrier; (h) removing part of the chip and part of the molding compound; (i) forming a second redistribution layer; and (j) removing the second carrier. Therefore, the second redistribution layer enables the stackable package to have more flexibility to be utilized.

Abstract: The present invention relates to a semiconductor device with a plurality of mark through substrate vias, comprising a semiconductor substrate, a plurality of original through substrate vias and a plurality of mark through substrate vias. The original through substrate vias and the mark through substrate vias are disposed in the semiconductor substrate and protrude from the backside surface of the semiconductor substrate. The mark through substrate vias are added at a specific position and/or in a specific pattern and serve as a fiducial mark, which facilitates identifying to the position and direction on the backside surface. Thus, the redistribution layer (RDL) or the special equipment for achieving the backside alignment (BSA) is not necessary.

Abstract: The present invention relates to a semiconductor device and a semiconductor package having the same. The semiconductor device includes a conductive element. The conductive element is disposed on a protruded conductive via and liner, and covers a sidewall of the liner. Whereby, the conductive element can protect the protruded conductive via and liner from being damaged. Further, the size of the conductive element is large, thus it is easy to perform a probe test process.

Abstract: The present invention relates to a semiconductor element having conductive vias and a semiconductor package having a semiconductor element with conductive vias and a method for making the same. The semiconductor element having conductive vias includes a silicon substrate and at least one conductive via. The thickness of the silicon substrate is substantially in a range from 75 to 150 ?m. The conductive via includes a first insulation layer and a conductive metal, and the thickness of the first insulation layer is substantially in a range from 5 to 19 ?m. Using the semiconductor element and the semiconductor package of the present invention, the electrical connection between the conductive via and the other element can be ensured, and the electrical connection between the silicon substrate and the other semiconductor element can be ensured, so as to raise the yield rate of a product.

Abstract: A semiconductor structure includes a plurality of thermal vias and a heat dissipation layer disposed at a periphery of a back surface of a lower chip in a stacked-chip package. This arrangement improves solderability of a subsequently-bonded heat sink. Additionally, the thermal vias and the heat dissipation layer provide an improved thermal conduction path for enhancing heat dissipation efficiency of the semiconductor structure. A method for manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor package structure including a substrate, a first chip, a second chip, and an interposer is provided. The substrate has a carrying surface and an opposite bottom surface. The first chip disposed on the carrying surface has a first surface and an opposite second surface. The second surface faces the substrate. The first chip has a plurality of through silicon vias (TSVs) and a plurality of first pads and second pads on the first surface. The first pads are electrically connected to the corresponding TSVs. The TSVs are electrically connected to the substrate. The second chip disposed above the first chip exposes a portion of the first surface. The second chip is electrically connected to the corresponding TSVs. The interposer is disposed on the first surface. Top surfaces of the interposer and the second chip are substantially aligned with each other. The interposer is bonded to the second pads.

Abstract: A microelectromechanical system package includes a chip carrier, a first microelectromechanical system chip, a silicon cover, a layer of metal, a plurality of first bonding wires and a sealant. The first microelectromechanical system chip is positioned on the chip carrier and has an active surface, and an active area on the active surface. The layer of metal is formed on the upper surface of the cover. The first bonding wires electrically connect the active surface of the first microelectromechanical system chip to the chip carrier. The sealant is formed on the chip carrier to encapsulate the first microelectromechanical system chip and the first bonding wires.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.

Abstract: A semiconductor structure, a method for manufacturing a semiconductor structure and a semiconductor package are provided. The method for manufacturing a semiconductor structure includes the following steps. Firstly, a silicon substrate is provided. Next, a part of the silicon substrate is removed to form a ring hole and a silicon pillar surrounded by the silicon pillar. Then, a photosensitive material is disposed in the ring hole, wherein the photosensitive material is insulating. After that, the silicon pillar is removed, such that the ring hole forms a through hole and the photosensitive material covers a lateral wall of the through hole. Lastly, the conductive material is disposed in the through hole, wherein the outer surface of the conductive material is surrounded by the photosensitive material.

Abstract: A package process is provided. The package process includes: disposing a semiconductor substrate on a carrier, wherein the semiconductor substrate has plural contacts at a side facing the carrier; thinning the semiconductor substrate from a back side of the semiconductor substrate and then forming plural through silicon vias in the thinned semiconductor substrate; forming plural first pads on the semiconductor substrate, wherein the first pads respectively connected to the through silicon vias; bonding plural chips to the semiconductor substrate, wherein the chips are electrically connected to the corresponding pads; forming a molding compound on the semiconductor substrate to cover the chips and the first pads; separating the semiconductor substrate and the carrier and then forming plural solder balls on the semiconductor substrate; and sawing the molding compound and the semiconductor substrate.

Abstract: The present invention relates to a method for forming a via in a substrate which includes the flowing steps of: (a) providing a substrate having a first surface and a second surface; (b) forming an accommodating groove and a plurality of pillars on the first surface of the substrate, the accommodating groove having a side wall and a bottom wall, the pillars remaining on the bottom wall of the accommodating groove; (c) forming a first insulating material in the accommodating groove and between the pillars; (d) removing the pillars so as to form a plurality of grooves in the first insulating material; and (e) forming a first conductive metal in the grooves. As a result, thicker insulating material can be formed in the via, and the thickness of the insulating material in the via is even.